International Business Machines Corporation

Other

Charles R Hoffman

Hayden C Cranford, Jr

Geoffrey B Stephens

Eugene R Bukowski, Jr

John E Gersbach

Philip H Sutterlin

Kenneth James Barker

Ilya I Novof

John M Mullen

William Burrell Nunnery

David E Conner

Phillip R Epley

Ronald L Coburn

Melvin T Laakso

Daniel Willaim Johnson

Douglas E Gill

H Clay Cranford, Jr

Jaideep Prakash

A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.

Method and system for fast ethernet serial port multiplexing to reduce I/O pin count

A process friendly precision voltage generator for use in a digital/analog system or the like, includes a modified phase lock loop (MPLL) and a frequency control system for adjusting the frequency of the MPLL until a desired reference voltage is obtained at an output node of the loop filter. The frequency of the phase lock loop is then locked to the frequency, at which the desired reference voltage has been obtained.

CMOS on-chip precision voltage reference scheme

There is disclosed a one piece coin holder having a main flat body, a central obstruction and openings at both ends suitable for insertion or egress of a predetermined number of coins. The open ends define a cavity with a slightly larger diameter than said coin but flexible protrusions are configured at said open ends in such a manner so as to trap said coin per it's diameter. The afore mentioned cavities would also hold said coins in a flat manner employing tabs which extend inward from the upper edge of said cavity walls defining an aperture portion. Said cavities would have dimensions consistent with those needed to hold new coins or ones with worn diameters and/or thickness'. There are also alignment rails Incorporated along the under side to aid in the installation process.

Portable coin holder and dispenser

A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal. Since multiple diodes are connected in series and their voltage drops are added together, the diodes also do not draw current from the network when the transceiver is powered down.

Single-port network node transceiver with powered-down protection

A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Reliable clock source having a plurality of redundant oscillators

The internal electrical noise generated by circuits of a VLSI chip is controlled by separating the logic circuit substrate contacts from the logic circuits ground contacts. A separate return path interconnects each contact to card ground. Further noise reduction is achieved by providing a void region between the noise generating devices and the 'quiet' devices. A substrate contact ring is provided in the void region. The substrate contact ring is connected by a separate path to card ground.

Substrate noise coupling reduction for VLSI applications with mixed

An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output. Control logic is used to identify the slope of the equalizer gain function at which total signal degradation is minimized. The control signal, which corresponds to this identified slope, is applied to the equalizer in real time to maintain minimum total signal degradation at the equalizer output.

Adaptive equalization and regeneration system

A high current CMOS circuit including a raised cosine signal generator for generating a raised cosine signal waveform and an input circuit arrangement for controlling the raised cosine signal generator is described. The raised cosine signal generator includes an output node to which a controlled chain of CMOS inverters are connected. The input circuit arrangement accepts an input signal, converts it into appropriate signals which drive respective inverters so that simultaneous conduction of inverter pairs is prevented. The off chip driver (OCD) minimizes ground bounce, electrical noise and radiation problems caused by large current transients or spikes (di/dt) that usually accompany such circuits.

Sinusoidal signal generator

Described is a circuit arrangement for controlling peak transient current on data buses of VLSI chips. The circuit arrangement includes a phase lock loop (PLL) with a voltage control oscillator (VCO) made up of high speed inverter circuits that generate very short time interval pulses that are used to control the switching sequence of drivers onto the buses. As a result, the transients are distributed over a relatively short time interval and data throughput on the buses is not adversely affected.

Current transient reduction for VLSI chips

An improved CMOS signal magnitude detector (SMD) for accurately quantifying the peak-to-peak magnitude of a received signal is disclosed. The SMD includes a precision gain amplifier, positive and negative peak detectors and a switched capacitive amplifier. The recited components are coupled to form a combination circuit arrangement which receives a differential signal and outputs a single ended signal which is compared with a reference signal to provide a control signal when the differential signal is of a sufficient peak to peak voltage magnitude. The control signal may be used to gate the differential signal and generate an output signal representative of received data.

CMOS signal threshold detector

A precision gain circuit arrangement for amplifying analog type signals is fabricated on an integrated chip with digital devices in a CMOS process. The circuit arrangement includes a high gain operational amplifier with a series connected pair of FET devices setting a reference voltage (V.sub.ref) at the inverting input of the operational amplifier and a feedback circuit including a parallel connected pair of FET devices and a biasing FET for said pair set the gain of said circuit arrangement.

CMOS precision gain amplifier

A process insensitive reference voltage generator includes a first and second identical FET devices coupled in a parallel configuration with a first biasing network, of FET devices, interconnecting the substrate terminal of the first FET device to a first node formed between a positive voltage supply and ground potential. The control terminal is connected to a second node whose voltage potential is different from that of the first node. The substrate terminal of the second FET device is connected to the source terminal. The source terminals of both FET devices are connected to the respective input terminals of an operational amplifier whose output is connected to the control terminal of said second FET device.

CMOS reference voltage generation

Described is a capacitive structure that can be fabricated with a digital MOS (Metal Oxide Semiconductor) process. The capacitive structure is comprised of two enhancement mode FET devices electrodes connected in series via their gate electrodes. The source and drain electrodes of each FET device are connected together. A third FET device, biased to operate within the linear or resistive region of its characteristic curve, is connected to the gate electrodes of the enhancement mode FET devices. The structure provides a voltage independent capacitor.

Bias scheme for achieving voltage independent capacitance

A differential voltage, set by threshold differences of a natural FET and an implanted FET, is amplified by a switched capacitor amplifier and filtered by a filtering circuit to provide an accurate reference voltage that is independent of temperature, process variation and power supply voltage changes.

CMOS Precision voltage reference generator

A non-volatile EAROS (Electrically Alterable Read Only Storage) memory array with fast reading and writing capability and a minimized cell size. Each cell of the array is composed of a floating gate first FET and a standard second FET connected in series between a reading bit line and a programming bit line for the row in which the cell is located. The floating gate of the first FET is connected through a capacitor to the common connection point between the first and second FET. DEIS (Dual Electron Injection Stack) material is used for the dielectric of a capacitor lying above the floating gate of the first FET. In programming the cell, a positive charge is stored on the floating gate of the first FET. When the cell is erased, the charge on the floating gate is reduced to zero, or at most a small negative charge. Because no large negative charge is stored on the floating gate, the voltages which can be applied to the diffusions of the cell are reduced, and thereby the cell area is correspondingly reduced.

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Raleigh, NC, United States of America

Charles R Hoffman