Xilinx, Inc.

Other

Fairchild Camera and Instrument Corp.

Xilink, Inc.

Charles R Erickson

Philip M Freidin

Kerry M Pierce

Edmond Y Cheung

Stephen M Trimberger

John E Mahoney

Chih-Tsung Huang

Douglas P Wieland

Lawrence Cy-Wei Hung

Robert O Conn

Peter H Alfke

Brian D Erickson

Tsung-Lu Syu

Alok Mehrotra

Lois D Cartier

Bernard J New

Steven Hennick Kelem

Khue Duong

Hung-Cheng Hsieh

Hemraj K Hingarh

William S Carter

Danesh Tavana

Krishna Rallapalli

William A Wilkie

Victor A Holen

Dan Wilnai

Peter W Verhofstadt

Ross H Freeman, Deceased

Hung-Cheng Hsieh, Deceased

By William Carter, Administrator

Kenneth E Leeds

Robert Moeckel

A concave-type spinner blade and lure body assembly for use with fishing lures that generates mechanical energy to rotate the lure body to attract fish is provided herein. The spinner blade is connected to the lure body by a connector that freely rotates around the lure's spindle. The lure body is suspended from the lure spindle by a plurality of rotational elements that are housed within the lure body. The rotational mechanical energy causes the lure body to rotate thereby producing an effect that attracts fish. The present invention can be used with trolling or casting lures used in bays, rivers, lakes, oceans, and estuaries to catch a wide variety of fresh and saltwater fish.

Rotating spinner blade assembly for fishing lures

A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.

Encryption of configuration stream

A structure for providing clearing/programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops. One method for clearing and programming a programmable logic device includes arranging a plurality of memory cells in sets, clearing the sets in a first spatial sequence, and programming the sets in a second spatial sequence. Sets of memory cells could include columns of memory cells, each column having an associated storage element. In this manner, a plurality of columns of memory cells can be cleared or programmed in any predetermined order. Thus, a method for programming a logic device may include programming a plurality of columns of memory cells in a first direction, and then programming a another plurality of columns of memory cells in a second direction. A reverse order is preferably used for clearing that logic device. Note that within one plurality of columns, any spatial sequence could be provided.

Configuration logic to eliminate signal contention during reconfiguration

A method and structure for testing static signal levels on an integrated circuit device using an electron beam deflection device. Each static signal is applied to a first terminal of a switch, such as an AND gate, an OR gate, or a pass transistor. An alternating control signal of approximately 1 MHz is transmitted to a second terminal of the switch such that the switch generates an output signal that is either constant (if the static signal is at a first level), or has a frequency equal to that of the alternating control signal (if the static signal is at a second level). The output signal is transmitted to a pad located on an exposed surface of the integrated circuit, where an electron beam deflection device is utilized to determine the static signal level by detecting the presence or absence of an alternating signal. A method for determining the voltage level of a signal includes applying the signal to the gate of a transistor and an alternating control signal to an input terminal. An electron beam deflection device is then utilized to measure the voltage level of a signal generated at an output terminal of the transistor. The voltage level of the signal is then calculated by adding the measured voltage level and a threshold voltage of the transistor.

Method and structure for viewing static signal levels on integrated

A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a corresponding cell access transistor. A row access circuit is coupled to the row lines. To re-program a first set (but not a second set) of configuration memory cells in a column, the row access circuit initially pre-charges each of the row lines, and then provides configuration data values on a first set (but not a second set) of the row lines. All cell access transistors in the column are coupled to a column select line. To avoid losing data in any memory cell, a relatively low read voltage, followed by a higher write voltage, is applied to the column select line. When the read voltage is applied to the column select line, the associated cell access transistors are weakly turned on. As a result, the row lines are charged to states which correspond to the configuration data values stored by the configuration memory cells. Consequently, when the write voltage is subsequently applied to the column select line, configuration data values stored by the second set of configuration memory cells are not disturbed.

Partially reconfigurable FPGA and method of operating same

An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

Configurable parallel and bit serial load apparatus

A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional 'high' and 'low' levels normally available.

Internal drive circuit providing third input pin state

Configuration stream encryption

An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins. The input interface contains two multiplexers which drive the pull-up and pull-down devices, each multiplexer being coupled to receive inputs from programmable memory cells and having a common control line.

Input signal interface with independently controllable pull-up and

A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ('FPGA'). In one embodiment, the memory device is a Read-Only Memory ('ROM') that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

Structure and method for reading blocks of data from selectable points

In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Circuit for testing pumped voltage gates in a programmable gate array

A scan lookahead skip structure that allows a programmable number of test bits, I/O blocks, flip-flops, or columns to be skipped. One embodiment of the structure includes multiplexers to skip the scan paths for several adjacent I/O blocks, flip-flops, or columns, thereby reducing the number of clock cycles and overall delay required to utilize the scan path.

Lookahead structure for fast scan testing

An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

Method and structure for loading data into several IC devices

Growing community of inventors

Fremont, CA, United States of America

Charles R Erickson