Hewlett-packard Company

Koninklijke Philips Corporation N.v.

Other

Agilent Technologies, Inc.

Charles R Dowdell

Ruby B Lee

Ronald D Larson

Bryan G Prouty

Joel D Lamb

Michael P Anthony

Larry Jay Thayer

Joseph R Fallon

Daniel Gerard Maier

Theodore Philip Fazioli

Rachel M Kinicki

Steven C Leavitt

Leon Sigal

A portable, configurable and scalable ultrasonic imaging system uses a phased ultrasonic transducer array coupled to a portable, configurable and scalable ultrasonic processor to develop ultrasonic images. When used in conjunction with a sector phased array, the portable, configurable and scalable ultrasonic imaging system uses a processing channel associated with each element in the transducer array to develop the ultrasonic image. When used with a linear or curved linear transducer array, the portable, configurable and scalable ultrasonic processor uses fewer processing channels than transducer elements to develop the ultrasonic image. Since the portable, configurable and scalable ultrasonic processor is scalable, it is able to use a variety of processors, software and transducer arrays to develop a number of different ultrasonic output images. The portable, configurable and scalable ultrasound imaging system includes a scalable architecture and includes alternative software configurable imaging applications and operating modes, and includes modifiable processing algorithms and operating features.

Portable, configurable and scalable ultrasound imaging system

A software program executing externally to an ultrasound imaging device. The software program enters user control values for the ultrasound imaging device and calculates parameters based on the entered user control values. The parameters are then transferred to and stored in the ultrasound imaging device. The ultrasound imaging device includes parametrically defined machines controlled by the stored parameters to generate ultrasound images.

Configuration tool for use in ultrasound imaging device

An ultrasound system incorporating the invention includes a front end that converts ultrasound backscatter signals to lines of digital data values. Those data values are then fed, under control of a front end controller, to plural processing modules which convert them into video displayable data. A memory is utilized to store processed results of each of the plural processing modules and operates as a shared memory that enables the various processing modules to communicate data therebetween. A memory controller enables each respective one of the plural processing modules to access processed results from the shared memory that were stored therein by a processing module whose function preceded, in time, the processing module performing the access. Thereafter, the processing module operates upon the data and writes it back to the shared memory, for use by a succeeding one of the plural processing modules.

Ultrasound system employing a unified memory

A method and apparatus is provided for interleaving frame buffer controllers in two dimensions. Each frame buffer controller includes an edge stepper, a subspan stepper and a span stepper. The subspan stepper separates each span line into a plurality of parts. Each frame buffer controller provides pixel data for certain parts of the span line. The parts are defined by a start value, a stop value and a starting color value.

System and method for triangle rasterization with frame buffers

A computer graphics system utilizes caching of pixel Z values to improve rendering performance. Apparatus for updating the Z values corresponding to pixels of a computer graphics display includes a memory for storing current Z values representing depths at corresponding pixel locations, a Z cache for storing a subset of the current Z values which are stored in the memory, and a comparator for comparing a new Z value with a corresponding current Z value and indicating a pass when the new Z value satisfies a predetermined criteria. The current Z value is read from the Z cache when the current Z value is stored in the Z cache and is read from the memory when the current Z value is not stored in the Z cache. The new Z value is written into the Z cache when the comparator indicates a pass. Each cache entry preferably includes a tile of current Z values corresponding to pixels having a predefined relationship. Different tile configurations may be selected for optimum rendering performance.

Computer graphics system using caching of pixel Z values to improve

A N-bit by N-bit multiplication apparatus having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention allows a sequence of n-bits from the N-bit by N-bit multiply result to be stored into an N-bit wide register. N+1 to 1 multiplexors are utilized to select which of the multiply result bits are stored into the result register in response to a computer instruction. The second preferred embodiment utilizes multiplexors having fewer than N+1 inputs to select discrete subsets of the multiply result bits for storage into the N-bit wide result register. In this manner, less complex multiplexors are required which take less chip area to implement. The third preferred embodiment utilizes multiple sets of multiplexors to select multiple subresults generated by a parallel multiplication operation. The multiple subresults are stored in a single result register. By allowing subresults to be selected and stored as part of the multiply operation, a multiply apparatus according to the present invention is more time and instruction efficient than prior art devices.

Computer multiply instruction with a subresult selection option

A computer instruction and apparatus for performing a N-bit by N-bit multiplication and having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention allows a sequence of n-bits from the N-bit by N-bit multiply result to be stored into an N-bit wide register. N+1 to 1 multiplexors are utilized to select which of the multiply result bits are stored into the result register in response to a multiply and select computer instruction. The second preferred embodiment utilizes multiplexors having fewer than N+1 inputs to select discrete subsets of the multiply result bits for storage into the N-bit wide result register. In this manner, less complex multiplexors are required which take less chip area to implement. The third preferred embodiment utilizes multiple sets of multiplexors to select multiple subresults generated by a parallel multiplication operation. The multiple subresults are stored in a single result register. By allowing subresults to be selected and stored as part of the multiply operation, a multiply apparatus according to the present invention is more time and instruction efficient than prior art devices.

Integer multiply instructions incorporating a subresult selection option

A scan converter incorporating a polygon span interpolator with main memory Z buffering. The span interpolator is initiated by instructions from a central processing unit (CPU), and when initiated, the span interpolator inerpolates input color and Z values in parallel. The span interpolator has its own state machine and can, once initiated, operate independent of the clock states of the CPU so that the CPU may process other data. Also, rather than using a dedicated memory as the Z buffer, the Z buffer shares main memory with the CPU. This allows the CPU to send pretranslated initial Z buffer addresses to the span interpolator when the span interpolator is initiated. Subsequent Z buffer addresses and color data addresses may be calculated in parallel with the input color and Z interpolations. Also, since the successive main memory and graphics addresses are known by the software, the memory controller of the invention allows data to be moved directly from main memory to the graphics address without CPU intervention and without having to pass the data through the data caches of the CPU. This greatly improves data transfer efficiencies since the cache penalties present in prior art software scan converters are not present.

Polygon span interpolator with main memory Z buffer

A system that clears a portion of a graphics display in synchronization with an electron beam scanning the face of the graphics display. When a clear operation for a window on the graphics display screen is received, the system compares the location of the beam with the window and determines whether an interference would occur if the window is cleared immediately. If no interference would occur, the window clear operation is immediately started. If an interference would occur, the system waits until the electron beam has scanned beyond the top of the window before starting the clear operation. Then, before clearing each scan line, the system waits until the beam has already scanned past the scan line being cleared.

Synchronous clear for CRT memory buffer

A system updates the z-values corresponding to pixels of a computer graphics screen. An integral part of the system comprises a controller/memory module which employs preliminary determinations as to whether or not a z-value has been previously stored for a pixel, multiple comparators, and partial read and write operations to achieve a significantly higher memory bandwidth. The bandwidth can be further increased by configuring a plurality of such modules in a parallel architecture.

Growing community of inventors

Nashua, NH, United States of America

Charles R Dowdell