Stmicroelectronics Gmbh

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (canada), Inc.

Charles Pilkington

Michel Langevin

Fabien Clermidy

Romain Lemaire

A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Network interface for a SoC comprising an improved communication controller

A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes a hardware concurrency engine coupled to the plurality of processors. The concurrency engine is capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. The concurrency primitives could represent objects, and the processors may be capable of using the objects by reading from and/or writing to addresses in an address space associated with the concurrency engine. Each address may encode an object index identifying one of the objects, an object type identifying a type associated with the identified object, and an operation type identifying a requested operation involving the identified object.

Accelerator for multi-processing system and method

A processing system includes a plurality of processing resources capable of executing a plurality of objects. The objects include a client object and one or more server objects. The client object is capable of requesting a service provided by at least one of the one or more server objects. The processing system also includes at least one hardware engine capable of receiving a request for the service from the processing resource executing the client object, formatting one or more messages associated with the requested service, and communicating the one or more messages to the processing resource executing at least one of the one or more server objects that provides the requested service.

Accelerator for object-oriented communications and method

A processing system includes a plurality of processing resources capable of executing a plurality of objects. The objects include a client object and one or more server objects. The client object is capable of requesting a service provided by at least one of the one or more server objects. The processing system also includes a hardware object request broker capable of receiving one or more messages from the processing resource executing the client object and communicating the one or more messages to the processing resource executing at least one of the one or more server objects that provides the requested service. The one or more messages are capable of invoking the requested service.

Object request broker for accelerating object-oriented communications and method

A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption. A back pressure mechanism allows the ring hops on a given communications ring to address overflow conditions on that ring, and a request mechanism allows the ring hops on a given communications ring to request use of that ring to carry a packet communication.

Hyper-ring-on-chip (HyRoC) architecture

A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes at least one hardware scheduler capable of scheduling execution of the plurality of threads by the plurality of processors. The at least one hardware scheduler is capable of scheduling execution of the threads by performing instruction-by-instruction scheduling of the threads.

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Ottawa, Canada

Charles Pilkington