Sun Microsystems, Inc.

Charles Patton

Steven M Kurihara

A system and method for performing viewport clipping for multiple viewports using a pipeline. The pixel address coordinates are compared against boundaries of a first viewport window. The results of this comparison, along with the pixel address coordinates, are registered and passed on to the next pipeline stage. There, the pixel address coordinates are compared against the boundaries of a second viewport window. The comparison results are combined with those passed from the previous stage, and the results are again registered. This scheme is repeated until the pixel has been tested against all the viewport window boundaries, with the intermediate results being combined into a single result indicative of whether the pixel is to be passed to the subsequent stages of the graphics pipeline or clipped.

Pipelined 2D viewport clip circuit

A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N&#xd7;2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N&#xd7;N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)&#xd7;N region of bits from the N&#xd7;N block and load bits of the (N/2)&#xd7;N region into a set of pixel tag outputs in a first mode, and (b) select an N&#xd7;(N/2) region of bits from the N&#xd7;N block and load bits of the N&#xd7;(N/2) region into the set of pixel tag outputs in a second mode.

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Dublin, CA, United States of America

Charles Patton