Dell USA L P

Itaggit, Inc.

Charles P Zeller

David Altounian

Sara Fox

Darius D Gaskins

Terry J Parks

John J Pearce

James L Walker

Michael D Durkin

Craig S Jones

Steven D Gluskoter

Kendall C Witte

Eric W Schieve

Wai-Ming Richard Chan

Thomas H Holman, Jr

Jim Walker

Gary W Abbott

An item data management server having the capability to create a physical item data record for a physical item in the control of a user based upon a data object of an accessible collection. The item data management server presents a clone command query to the user terminal, and receives, in response, a clone command query response that corresponds to and identifies a data object having a plurality of attributes. The item data management server generates a cloned physical item data record based upon the data object. The cloned physical item data record includes at least a portion of the plurality of attributes of the data object, and a second plurality of attributes associated with the user. The item data management server generates a web page including the cloned physical item data record, and presents the web page to the user terminal.

Physical item data record creation via cloning a data object in an accessible collection

An item data management server with rapid item data entry to facilitate database population with physical item data records for physical items in the control of a user. The rapid item data entry includes receiving a media file with at least an image and/or a verbal description for a physical item in which the item data management server may create physical item data record.

Rapid item data entry for physical items in the control of a user in an item data management server

An item data management server having the capability to transfer information and records via a physical item data record of an item data management server. The physical item data record transfer and/or cloning facilitates ready maintenance and upkeep of the inventory of physical items to other users to facilitate community/trade, and also provides a feature for providing information relating to the physical items to third-party service providers, such as insurers, and to governmental authorities, such as in the event of theft, to aid in the recovery of the physical items, et cetera.

Transferring information and records via a data structure for a physical item in the control of a user

A item data management server having the capability to create a data tag from a physical item data record, where the physical item data record is based upon a physical item in the control of a user. The data tag creation facilitates the identification, maintenance and upkeep of the inventory of physical items, and also provides a feature for providing information relating to the physical items to the user/owner as well as to third-party service providers, such as insurers, and to governmental authorities, such as in the event of theft, to aid in the recovery of the physical items.

Data tag creation from a physical item data record to be attached to a physical item

An item data management server to capture, store, organize, and present information regarding a plurality of physical items in the control of a user. The item data management server is coupled to a user terminal via at least one data network.

Item data management over a data network for physical items in the control of a user

A item data management server having the capability to create a data tag from a physical item data record, where the physical item data record is based upon a physical item in the control of a user. The data tag creation facilitates the identification, maintenance and upkeep of the inventory of physical items, and also provides a feature for providing information relating to the physical items to the user/owner as well as to third-party service providers, such as insurers, and to governmental authorities, such as in the event of theft, to aid in the recovery of the physical items, et cetera.

Method and apparatus for selectively overriding a prepackaged power management driver of a portable personal computer so that data transmitted to the CPIU of the computer by a device, such as a &ldquo;real time&rdquo; serial communicators device connected thereto, is not lost during the CPUs latency &ldquo;wake up&rdquo; period following a CPU power-down operation. An override system stored in memory comprises an override flag which may be set or cleared by a user or the computer. If the override flag is set, then the power management system is prevented from reducing power to the CPU so that the occurrence of a CPU latency period and thus potential for loss of data is avoided.

Power management override for portable computers

A portable computer is provided with enhanced power management capabilities. The portable computer includes a power management system which makes a determination as to whether the computer is 'user attended' or 'user unattended' based upon the position of the display screen in one embodiment. If the display screen is open, then the computer is regarded as being 'user attended'. In this case, a first timeout delay of I/O inactivity is applied before the computer is permitted to enter a power saving suspend mode. However, if the display screen is closed, then the computer is regarded as being 'user unattended'. Is this situation, a second timeout delay of I/O inactivity is applied before the computer is allowed to enter the power saving suspend mode. The second timeout delay is generally significantly shorter than the first timeout delay. This technique is found to significantly increase the reliability of I/O activities such as external communications with the computer when the computer is 'user unattended'.

Computer system with unattended operation power-saving suspend mode

A computer system having a central processing unit ('CPU'), a main memory divisible into allocable units, a secondary storage unit and an operating system for allocating the allocable units to tasks for use thereby is provided with a suspend circuit for creating an optimized compressed image of data in the main memory. In a first embodiment, the suspend circuit comprises: (1) a circuit for initiating execution of a reducing task on the CPU, the reducing task requesting the operating system to allocate unallocated ones of the allocable units to the reducing task, (2) a circuit for storing a bit pattern in the allocable units allocated to the reducing task, the bit pattern chosen to optimize performance of a data compression process and (3) a circuit for executing the data compression process to store a compressed image of the main memory in the secondary storage unit, the bit pattern allowing a size of the compressed image to be reduced and a time required to compress and store the compressed image to be minimized. In a second embodiment, the unallocated allocable units are neither compression-optimized, compressed nor stored. Rather, the reducing task creates a record of all allocated units and the data compression process acts on only those allocated units identified in the record.

Circuit and method for optimizing creation of a compressed main memory

A peripheral bus interface unit is provided that includes a data storage unit for temporarily storing data written from a peripheral unit, and a control unit that executes a write cycle on a system bus to transfer the data into a system memory. The control unit blocks certain communications, such as polling and interrupt communications between a microprocessor and the peripheral device if data temporarily stored within the data storage unit has not yet been transferred to the system memory. In addition, depending upon whether a complete line of data is to be transferred during the write cycle, the control unit either asserts or deasserts a snoop write-back signal. If the snoop write-back signal is asserted, a snoop write-back operation by, for example, a cache controller is allowed. If the snoop write-back signal is deasserted, a snoop write-back operation of the cache controller is suppressed. In one embodiment, a line monitor unit within the peripheral bus interface unit is employed to determine whether a full line of valid words are being transferred during a given cycle. An interrupt latch is also employed to detect an assertion of an interrupt signal generated by the peripheral unit when the peripheral unit has completed its requested transfer. After the control unit causes the corresponding data stored within the data storage unit to be written out to system memory, the asserted interrupt signal is forwarded to a microprocessor via the system bus.

Cache-based computer system employing a peripheral bus interface unit

A digital processor system is disclosed that employs a bus bridge interfacing a primary bus to a secondary bus and which includes a transaction backoff signal line that provides an economical method of providing split transactions between the busses, of preventing deadlock situations between the busses, and of providing strong lock ordering across the busses. A primary bus master is backed-off the bus if it is attempting to access a device resident on the secondary bus and if mastership of the secondary bus cannot be attained by the bus bridge within a certain latency. The bus bridge further implements a method of prefetching read data from a device resident on the secondary bus in response to a primary bus master being backed-off the primary bus during a read operation.

Multi-purpose usage of transaction backoff and bus architecture

An interconnection system for electronic devices includes an internal master connecting terminal which is arranged to receive and mate with one of a plurality of available modular interfacing devices. The electronic device includes a system of internally arranged support and housing cavities which are graduated in size to house and support the modular interfacing devices and provide a uniform and contiguous output interface for connection to other electronic and peripheral devices. The modular interfacing devices are designed to accomodate the inclusion of various bus arrangements as well as additional components and circuitry, both active and passive.

Internal/external modular interface

A cache-based computer system is provided with a snoop control circuit that implements a write-back suppression technique. The snoop control circuit controls the write-back and invalidation of dirty data within a cache memory during a DMA write operation to maintain the integrity of data within the computer system. If an alternate bus master initiates a burst transfer cycle that does not encompass an entire line of valid data, the alternate bus master asserts a snoop write-back signal that causes the snoop control circuit to effectuate the write-back to system memory of a corresponding dirty line in the cache memory. Integrity of the data within the system is thereby maintained. On the other hand, if the alternate bus master initiates a burst transfer cycle that does encompass an entire line of valid data, the altemate bus master deasserts the snoop write-back signal. When the snoop write-back signal is deasserted, the snoop control circuit advantageously suppresses the write-back of the corresponding dirty data in the cache memory, thereby attaining reduced traffic on the system bus. Since the DMA operation involved the transfer of an entire line of valid data, the integrity of data is maintained even though the write-back of the dirty line was suppressed. As a result, the bandwidth of the computer system may be improved and the overall performance of the system may be enhanced.

Cache-based computer system employing a snoop control circuit with

A system for reducing the amount of power consumed by a battery operated computer device is disclosed. A microcontroller continuously monitors the activity of at least one I/O device and sets an activity state variable (ASV) associated with the I/O device accordingly. Upon each the expiration of a preselected time period, the microcontroller examines the state of the ASV to determine whether the I/O device was active during the expired time period. If so, the I/O device is caused to operate in a full power mode; otherwise, the I/O device is caused to operate in a reduced power consumption mode. In one embodiment, the I/O device is capable of operating in more than one reduced power consumption mode, in which case, responsive to a determination that the I/O device was not active during the expired time period, the I/O device is caused to operate in the next lowest power consumption mode. In an alternative embodiment, the frequency with which timer interrupts are generated is automatically adjusted after the expiration of each time period.

System for reducing power consumption in computers

A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a first data width. Also connected to the data bus is at least one I/O device configured to handle data units of a second data width. By adjusting the width of the data being transferred to match the width of the receiving device or bus, data may be transferred between devices of differing width. To adjust the width, control means are provided which modify the route along which data bytes are transferred based upon the width of the transferring and receiving devices and the direction of transfer are provided.

Growing community of inventors

Austin, TX, United States of America

Charles P Zeller