Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Other

Honeywell Bull, Inc.

Charles P Ryan

William A Shelly

Marion G Porter

Wayne R Buzby

Russell Wayne Guenthner

Ronald W Yoder

John E Wilhite

Lowell D McCulley

Patrice Brossard

Thomas H Howell

Robert W Norman, Jr

Leonard G Trubisky

James L King

Robert J Baryla

Eric Earl Conway

Ron Yoder

Stephen A Schuerich

Andrew Y Pan

David W Rolston

A multiprocessor write-into-cache data processing system includes a feature for preventing hogging of ownership of a first gateword stored in the memory which governs access to a first common code/data set shared by processes running in the processors by imposing first delays on all other processors in the system while, at the same time, mitigating any adverse effect on performance of processors attempting to access a gateword other than the first gateword. This is achieved by starting a second delay in any processor which is seeking ownership of a gateword other than the first gateword and truncating the first delay in all such processors by subtracting the elapsed time indicated by the second delay from the elapsed time indicated by the first delay.

Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.

Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment

Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache 'hit' is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.

High integrity cache directory

In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least four processors having respective private caches with the first and second private caches being coupled to the first shared cache and to one another via a first internal bus, and the third and fourth private caches being coupled to the second shared cache and to one another via a second internal bus; method and apparatus for preventing hogging of ownership of a gateword stored in the main memory and which governs access to common code/data shared by processes running in at least three of the processors. Each processor includes a gate control flag. A gateword CLOSE command, establishes ownership of the gateword in one processor and prevents other processors from accessing the code/data guarded until the one processor has completed its use. A gateword OPEN command then broadcasts a gateword interrupt to set the flag in each processor, delays long enough to ensure that the flags have all been set, writes an OPEN value into the gateword and flushes the gateword to main memory. A gateword access command executed by a requesting processor checks its gate control flag, and if set, starts a fixed time delay after which normal execution continues.

Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment

In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a &ldquo;set gate control flag&rdquo; command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor. Optionally, the processor so acquiring ownership broadcasts a &ldquo;reset gate control flag&rdquo; command to all processors when it has acquired ownership of the gate control word.

Gateword acquisition in a multiprocessor write-into-cache environment

In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors ( ) sharing an L2 cache ( ) differs from the time it takes for those signals to travel between processors ( ) not sharing the same L2 cache ( ). This difference, or DELTA, is dynamically computed by computing ( ) the time it takes for a invalidate cache line cache command to travel between a local processor ( ) and a master processor ( ). This computation ( ) is then made for the time it takes the signal to travel between a remote processor ( ) and the master processor ( ). The difference ( ) is the DELTA value in cycles. This DELTA value can then be utilized to bias delay values when exhaustively testing the interactions among multiple processors in a CC-NUMA environment ( ).

Method and apparatus for determining CC-NUMA intra-processor delays

A processor ( ) contains a Trace RAM ( ) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller ( ) and the arithmetic (AX) processor ( ). A second trace mode selectively traces full operand words that result from microcode instruction ( ). Each microcode instruction word ( ) has a trace enable bit ( ) that when enabled causes the results of that microcode instruction ( ) to be recorded in the Trace RAM ( ).

Data processing system processor dynamic selection of internal signal tracing

A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe is used to selectively step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline. A comparison, at a predetermined phase along the delay pipe, determines if the information set identifies, as currently resident in the instruction buffers, a target address that matches the target address in the transfer instruction traversing the pipeline. If there is a finding that the information set traversing the delay pipe identifies a target address in the instruction buffers that matches the target address in the transfer instruction traversing the pipeline and there is an indication of TRA-GO from the pipeline, the instruction identified by the target address is sent to the pipeline from the instruction buffers rather than from the instruction cache.

Pipelined central processor managing the execution of instructions with proximate successive branches in a cache-based data processing system while performing block mode transfer predictions

In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by utilizing a plurality of sets of registers maintained in a round-robin system. Whenever a transition is made to a higher security environment, a switch is made to a different set of registers. Then, when a transition is made back to the lower security environment, a switch is made back to the previous set of registers. Writes to memory copies of registers are detected, and only those registers whose memory copies have been modified are restored from the memory copy.

Process switching register replication in a data processing system

Interactions among multiple processors (,) are exhaustively tested. A master processor (,) retrieves test information for a set of tests from a test table (,). It then enters a series of embedded loops, with one loop for each of the tested processors (,). A cycle delay count for each of the tested processors (,) is incremented (,) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (,). In each such test (,), the master processor (,) sets up (,) each of the other processors (,) being tested. This setup (,) specifies the delay count and the code for that processor (,) to execute. When each processor (,) is setup (,), it waits (,) for a synchronize interrupt (,). When all processors (,) have been setup (,), the master processor (,) issues (,) the synchronize interrupt signal (,). Each processor (,) then starts traces (,) and delays (,) the specified number of cycles. After the delay, the processor (,) executes its test code (,).

Method and apparatus for exhaustively testing interactions among multiple processors

A processor (,) in a data processing system (,) provides a DELAY instruction. Executing the DELAY instruction causes the processor (,) to a specified integral number of clock (,) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.

Data processing system processor delay instruction

Two instructions are provided to synchronize multiple processors (,) in a data processing system (,). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (,) to all of the active processors (,) in the system (,). Processors (,) wait for receipt of the synchronize signal (,) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (,) is activated at the next clock cycle after receipt of the interrupt signal (,). An optional timeout value is provided to protect against hanging a waiting processor (,) that misses the interrupt (,). Whenever the WSYNC instruction is activated by receipt of the interrupt (,), a trace is started to trace a fixed number of events to an internal Trace Cache (,).

Apparatus for synchronizing multiple processors in a data processing system

A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe, constituting serially-coupled registers, is used to step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline. A comparison, at a predetermined phase along the delay pipe, determines if the information set identifies, as currently resident in the instruction buffers, a target address that matches the target address in the transfer instruction traversing the pipeline. If there is a finding that the information set did identify a target address in the instruction buffers that matches the target address in the transfer instruction traversing the pipeline and there is a TRA-GO from the pipeline, the instruction identified by the target address is sent to the pipeline from the instruction buffers rather than from the instruction cache.

Synchronization of branch cache searches and allocation/modification/deletion of branch cache

A data processing system which employs a cache memory feature and a method for lowering the cache miss ratio for called operands in the data processing system are disclosed. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The efficiency of the method and apparatus is improved by managing the priority of the block stored in cache memory such that a block received from main memory as a result of a prediction is forced to 'least recently used' (LRU) status. In this manner, if the prediction has been incorrect, the incorrectly predicted block is replaced by the next block summoned from main memory rather than conventionally working its way down a priority stack before it is discarded.

Data processing system and method using cache miss address prediction

In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The cache miss prediction mechanism is only selectively enabled during cache 'in-rush' following a process change to increase the recovery rate; thereafter, it is disabled, based upon timing-out a timer or reaching a hit ratio threshold, in order that normal procedures allow the hit ratio to stabilize at a higher percentage than if the cache miss prediction mechanism were operated continuously.

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Phoenix, AZ, United States of America

Charles P Ryan