Allegro Microsystems, LLC

Charles Myers

Adam Lee

Shunming Sun

Andrew S Huntington

Leo Filippini

Systems, methods, and circuits utilize one or multiple data-stream watchdog codes for verifying a temporal state of data from a sensor system. A data-stream watchdog system can includes a sensor system configured to detect physical phenomena and produce corresponding output signals; a memory structure configured to store the output signals as sequential data on a repeating cycle, a watchdog code generator configured to insert a watchdog code into the stored sequential data and update the watchdog code periodically, and a data transmitter configured to receive the sequential data with included watchdog code from the memory structure and transmit the sequential data with the included watchdog code over a physical data channel each cycle of the repeating cycle. An application system receives the data and a watchdog code checker checks whether the watchdog code in the sequential data is correct and produces an error indication when the watchdog code is incorrect.

Data stream watchdog injection

Methods and apparatus for a detector system having a photodetector and an amplifier to amplify the photodetector signal. A discriminator generates an active output signal when the output from the amplifier is greater than a threshold. An injection circuit is coupled to the input of the amplifier. The injection circuit is configured to selectively inject a test pulse that mimics a pulse from the photodetector for verifying operation of the detector system.

Programmable active pixel test injection

Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.

Delay-locked-loop timing error mitigation

Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

Arrayed time to digital converter

Methods and apparatus for nonuniformity correction (NUC) for a sensor having an avalanche photodiode (APD) array and an integrated circuit. The sensor can include anode bias control module, a passive mode module, and an active mode module. DC photocurrent from the APD array can be measured and used for controlling an anode reverse bias voltage to each element in the APD to achieve a nonuniformity correction level less than a selected threshold.

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Portland, OR, United States of America

Charles Myers