International Business Machines Corporation

Charles Meissner

Pedro Martin-de-Nicolas

Allon Adir

John Martin Ludden

Michael Timothy Saunders

Robert Walter Berry, Jr

Amir Nahir

Todd Swanson

Matthew Edward King

Gil Eliezer Shurek

Michael Edward Criscolo

Brad Lee Herold

Bryan Glen Hickerson

Michael E Weissinger

Dimtry Krestyashyn

Brenton Yiu

Elena Tsanko

Methods and systems for testing a functionality of a code modification operation are described. In an example, a processor can include a processor pipeline comprising one or more execution units. The processor pipeline can execute a first thread. The processor pipeline can further execute a second thread concurrently with the execution of the first thread. The second thread can be executed to modify the first thread using a code modification operation. The processor can further include a test module configured to validate a functionality of the code modification operation based on a result of the modified first thread.

Functional test of processor code modification operations

A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.

Method, apparatus and product for testing transactions

A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path. The re-direction instructions may be illegal instructions, which cause execution of an interrupt handler that performs the replacement.

Two pass test case generation using self-modifying instruction replacement

A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions. When discrepancies exist, the simulator is modified accordingly to match the hardware-identified operating conditions.

System and method of automating the addition of RTL based critical timing path counters to verify critical path coverage of post-silicon software validation tools

The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

Method and apparatus for determining the failing operation of a device-under-test

The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC value to determine if the electrical component passed or failed the test.

Method and apparatus for test case evaluation using a cyclic redundancy checker

Growing community of inventors

Austin, TX, United States of America

Charles Meissner