General Electric Company

Charles M Puckette

Walter J Butler

Gary Jude Saulnier

Chia-Chi Huang

Lewin T Baker

James R Whitten

Sanjay K Bose

George W Ellis

A transmitter location searching system produces fast, stable and accurate results in a multipath transmission environment by geometrically partitioning the monitored area into a plurality of cells and finding the optima of a total cost function at the centers of the cells. The original three-dimensional optimization problem is thus reduced to a one-dimensional problem. Based on this calculation, the cell providing the smallest cost is chosen as a new candidate cell which is divided into smaller cells and the minimum costs are calculated for each of these smaller cells. The cell that provides the smallest cost is chosen as the center of another new candidate cell. The process is iterated until a dimension of a new candidate cell is smaller than a predetermined threshold. By reducing the dimensions of each cell by a factor of two at each iteration, the algorithm converges rapidly.

Transmitter location searching system

A digital subharmonic sampling converter, for use in an analog IF signal demodulator and the like, includes: an analog-to-digital converter (ADC) means receiving the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to 4/(2n+1) times the IF signal frequency, where n is an integer greater than zero. A digital mixer means is used to convert the sampled data to baseband. The interleaved sequential in-phase I data words and quadrature-phase Q data words are then sorted into a pair of concurrent I and Q data word streams.

Digital subharmonic sampling down-converter

A digital data communications method and system combining frequency agility with a frequency-shift-keyed signal to transmit a unique code word representing a plurality of data states. Each code word comprises a plurality of chips, each of which is an integer subportion of the bit time interval in which one data bit is communicated. The multiple-chip word provides a frequency-hopped spread spectrum signal in which the nominal carrier frequency value is offset for transmitting binary data, or is offset in either frequency direction by different discrete amounts for transmitting multilevel digital data, to allow the data value to be properly decoded at a receiver even if the transmitter instantaneous frequency during at least one chip time interval is jammed by another signal. The frequency offset, can also be provided in complementary fashion during selected chip time intervals to even further encode the data bit being communicated and further reduce the probability of jamming. The multiple-chip code word, of normal or selected-chip-complemented form, modulates a carrier at the transmitter end. The FH-FSK carrier is demodulated at the receiver end by an inverse modulation process which converts the signal into a serial bit stream, for matched filtering transmission and reception apparatus of non-complemented and/or complemented chip-encoded words is described.

Method of, and apparatus for, frequency-hopped frequency-shift-keyed

An improved digital data demodulator, capable of properly detecting Manchester-encoded FSK received signals or chirped-frequency-modulated received signals, utilizes a multiplexer for switching the clock signals, to a pair of counters, from one of the mixing means receiving the input and phase-quadrature local reference signals, at a time essentially at the middle of each bit time interval expected for the incoming data signal, and is insensitive to time base jitter or other sources of timing error. In all embodiments, the transmission frequency and data bit rate are determined by externally-supplied reference frequencies, to allow a single demodulator to be utilized with a multiplicity of digital data signals having differing characteristics.

Binary signal demodulator with comparative value decision circuitry

A frequency-shift-keyed binary data signal demodulator utilizes a reference frequency equal to the arithmetic mean of the two tone frequencies corresponding to the two binary states of an FSK data signal. The frequency-acceptance bands of the FSK signals are varied by variation of the reference frequency. An auxiliary 'data valid' signal can be recovered along with the recovered binary data. A demodulator is also disclosed for providing maximum likelihood of detection of an FSK signal having a frequency shift which is a multiple of the bit rate.

Demodulator for frequency-shift-keyed binary data signals

A method for transmission of digital data utilizes a carrier frequency offset in a first frequency direction for a first binary condition, and offset in a second frequency direction for the remaining binary condition, at the start of a bit time interval. The carrier frequency is swept in a preselected frequency direction during each bit time interval, to produce a chirped frequency-shift-keyed waveform in the frequency domain, for transmission of each bit of binary data. Frequency-shift-keyed demodulation is utilized at a receiving end, with the receiver synchronized to the transmitter bit time interval, to recover the transmitted digital data. Apparatus for data transmission using this chirped frequency-shift-keyed modulation waveform is disclosed.

Method and apparatus for data transmission using chirped

A linear mixer, having essentially no spurious responses below the fifth harmonic of a local oscillator frequency, utilizes a balanced demodulator summation network having first and second inputs each receiving an RF input signal via an associated one of a pair of switches operated at the local oscillator frequency. The local oscillator waveform is selected to eliminate the third harmonic thereof, whereby a baseband signal output of the summation network is a signal having essentially zero magnitude responses at at least the second, third, fourth and sixth harmonics of the oscillator frequency. Digital circuitry to provide the required oscillator waveform is disclosed.

Linear mixer with reduced spurious responses

An excitation circuit is disclosed which is responsive to a trigger signal to drive a capacitive load with a controllable high frequency pulse burst. The pulse burst takes the form of a multiple cycle output signal which has a selectively variable high voltage determined by the supply voltage of the circuit. The output signal replicates and is coherent with the trigger signal applied to the circuit. The latter signal thus determines the pulse width and signal duration, i.e. the number of cycles, of the output signal. The circuit is particularly adapted to provide a programmable burst excitation for driving an ultrasound transducer or the like.

Variable excitation circuit

A phase shifter is disclosed which provides a reference-phase square-wave as a first output and a second square-wave of the same frequency as the reference-phase square-wave and having the phase thereof shifted, with respect to the reference-phase square-wave, synchronously by a phase increment which is programmable in steps equal to 360/2.sup.N degrees, where N is an integer equal to number of stages in a shift register receiving binary phase control information.

Digitally programmable phase shifter

An input circuit is disclosed for variably adapting the dynamic range of an ultrasonic frequency electrical signal to the dynamic range of a signal receiver to which the signal is applied. A band pass filter admits the appropriate band of signal frequencies to the receiver to provide optimum signal-to-noise conditions. A JFET device is shunted across the receiver input and its drain-to-source impedance is varied to control the peak voltage developed by the signal. Control of the impedance of the JFET device may be effected in a pre-programmed manner as a function of time, in response to the amplitude of the signal applied to the receiver input, or in response to both. In either case, the amplitude of the applied signal is constrained to remain substantially within the dynamic range of the receiver.

Adaptive input circuit

A charge transfer circuit of the type including first and second charge storage locations and a charge transfer transistor for transferring a plurality of discrete packets of charge from the first to the second charge storage location is disclosed. The charge transfer circuit includes circuitry for compensating for changes in a thermally induced leakage current such that the charge transfer transistor transfers a variable amount of charge from the first to the second charge storage location during each successive charge transfer operation such that the total amount of charge, i.e. the leakage charge plus the transferred charge packet, accumulated by the second charge storage location during each charge transfer operation, is a constant regardless of changes in the temperature or illumination of the transistor. In a second embodiment, changes in the magnitude of the thermally or optically induced leakage current are taken into account by adjusting the magnitude of an analog signal to which the total amount of charge stored in the second charge storage location is compared.

Charge transfer circuit with leakage current compensating means

A monolithic analog to digital converter having leakage current compensating circuitry is disclosed. First and second charge storage capacitors are formed in a single semi-conductor substrate. An analog signal to be converted and a reference signal are simultaneously applied to the first and second capacitors, respectively. Thereafter, a charge transfer circuit supplies the first capacitor with a plurality of discrete charge packets. The polarity of the charge packets is chosen so as to increase or decrease the voltage across the first capacitor in the direction of the voltage across the second capacitor. When the voltage across the two capacitors become equal, a differential comparator generates an output signal indicating the end of a conversion operation. The parameters of the first and second capacitors are chosen such that the amount of charge added to or subtracted from the second capacitor due to a thermally induced leakage current in the substrate is substantially equal to the amount of charge added to or subtracted from the first capacitor as the result of the thermally induced leakage current.

An analog-to-digital converter is described wherein an analog signal is converted to a digital equivalent thereof in a structure suitable for implementation in MOS form. The analog signal is converted to a quantity of charge which is duplicated by summing a plurality of substantially equal sized charge packets in an MOS charge storage location.

A/D Converter

A time-independent, dual-slope analog to digital converter is disclosed. During a first integration period, a predetermined number of charge packets having a first polarity and a magnitude proportional to the magnitude of an analog voltage to be converted are applied to a charge storage element. The first integration period is followed by a second integration period during which a second plurality of charge packets are applied to the charge storage element. The second plurality of charge packets each have a polarity opposite to that of the first plurality of charge packets and a predetermined, constant magnitude. The number of second charge packets required to return the charge stored in the charge storage element to its original value is indicative of the magnitude of the analog signals to be converted.

Dual-slope analog to digital converter

Improved isolation between the four-wire receive and transmit ports in a four wire-to-wire converter in a communication system is obtained by utilizing a tapped delay line network in an active hybrid circuit. The active hybrid circuit includes a first amplifier which terminates the four-wire receive channel in its characteristic impedance, amplifies the four-wire received signal, and excites a resistor network that terminates the two-wire channel in its nominal characteristic impedance. A second amplifier and a resistor circuit function as a weighted summer for nulling the received four-wire signal with the signal passing through the resistor network to obtain signal cancellation at the four-wire transmit port when the four-wire receive channel is activated. The tapped delay line network may be connected either between the first amplifier and resistor network or between the first amplifier and the received four-wire signal input of the second amplifier.

Growing community of inventors

Scotia, NY, United States of America

Charles M Puckette