At&t Bell Laboratories

Bell Telephone Laboratories

Charles M Lee

Masakazu Shoji

Donald E Blahut

Bernard T Murphy

Victor K Huang

Jonathan A Fields

An integrated circuit chip in which clock pulses are distributed to a plurality of circuits includes a pattern of trimmable elements such as capacitors or transistors. The capacitors or transistors are trimmed during manufacture in order, for example, to adjust clock skew.

Trimmable loading elements to control clock skew

A complementary MOS static EXCLUSIVE OR gate is formed by a PMOS logic network having a pair of cross-coupled PMOS transistors and an NMOS logic network having two parallel branches, each of the branches containing a separate pair of NMOS transistors connected in series.

Complementary field effect transistor EXCLUSIVE OR logic gates

A dynamic CMOS logic circuit for computing multiple AND functions contains a sequence of at least three successive stages controlled by the same timing signal, each stage having a logic network of driver transistors in which at most three such transistors are connected in series along any path through the network.

Dynamic CMOS logic circuits for implementing multiple AND-functions

A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals. If the second Control Code specifies reading, the contents of the selected register or control latch is provided at the Address/Data port. If the second Control Code specifies writing, data received at the Address/Data port is stored in the selected register. The IA function facilitates program development in the processor because it provides an efficient means for observing the internal machine states and register contents of the processor. Functional testing of the processor is also facilitated because the IA function increases the availability of the internal nodes of the processor chip for the application of test signals and for the observation of circuit responses.

Microprocessor architecture having internal access means

A transistor-transistor logic gate is described which uses a number of bipolar switching transistors clamped in several different ways. In particular to better adapt a bipolar switching transistor to high frequency, high temperature operation, the collectors of the various switching transistors are clamped in a variety of novel ways, each to achieve a collector voltage higher than that normally achieved by the conventional Schottky diode clamp connected between the base and collector.

Growing community of inventors

Berkeley Heights, NJ, United States of America

Charles M Lee