Apple Inc.

Charles M Flaig

William T Krein

James D Kelly

Steven G Roskowski

Dean M Drako

Michael L Regal

A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node. The state machine launches READs to the node only when an unallocated buffer slot is available to service the corresponding READ RESPONSE.

Method and apparatus for dynamic buffer allocation in a bus bridge for

A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.

Line data architecture and bus interface circuits and methods for

An interface between two buses in different clock domains. The interface includes a master buffer which is used for both master writes and slave reads. A control logic unit for each bus receives signals from a buffer manager which straddles the clock domains to gate latch pulses to the master buffer.

Master oriented bus bridge

Connectors on a microcomputer printed circuit board backplane receive slotted insertion of a plurality of device cards containing application specific integrated circuits (ASICs). Interconnection of the device card connectors is accomplished on the surface of the circuit board or internally with an electric line which interleaves the device card connectors providing increased conductor length between physically adjacent connectors, establishing an increased impedance level. The increased physical lengths of the intervening electric lines between the connectors provide increased impedance as seen by inserted device cards, which enhances the matching capabilities of the connectors.

Interleaved connector circuit having increased backplane impedance

To optimize system bus utilization in a computer system, a bus coordinator is included in the computer system to coordinate the transfer of information signals on the bus. Each time a source node wishes to transfer information to a destination node, the source node sends a request to the coordinator along with the identification of the destination node. Upon receiving this request, the coordinator determines whether the destination node has capacity to receive information signals. If the destination node has capacity, then the coordinator grants control of the system bus to the source node to allow the source node to send information signals to the destination node via the system bus. Otherwise, the source node is denied control of the system bus until the destination node has capacity to receive information signals. By granting control of the system bus to a source node only when the destination node has capacity to receive information signals, the coordinator ensures that no system bus time is wasted on unsuccessful information transfers. Thus, bus utilization is optimized.

System and method for coordinating access to a bus

A bus system uses separate clocks for arbitration and data transfer. The arbitration clock signal is used for synchronizing bus request and grant events, and the data clock signal is used for synchronizing data transmission and reception. In particular, the data clock signal, which is generated by a bus master node without any temporal relationship to the arbitration clock signal, is transmitted by the bus master node through the bus to a slave node, where the received data signal is synchronized with the data clock signal transmitted therewith.

Bus protocol using separate clocks for arbitration and data transfer

In a bus system including a bus, a plurality of nodes including a primary node, and a bus access coordinator, bus utilization efficiency is improved by operating the coordinator at the same clock frequency as the primary node. The primary node is the node in the bus system which accesses the bus most frequently. By running the coordinator synchronous with the primary node, the need for synchronization events between the two components is eliminated. Since the primary node accesses the bus most frequently, eliminating synchronization events with the primary node eliminates most of the synchronization events in the bus system. Thus, synchronization events are minimized which, in turn, improves bus utilization efficiency.

Method and system for improving bus utilization efficiency

A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state. If the bus request is reasserted within the extra cycle, the coordinator continues to maintain the bus grant signal in the asserted state so that no state change is experienced by the bus grant signal between the deassertion and the reassertion of the bus request signal. In this manner, consecutive bus requests are pipelined. To further increase the efficiency of the system, the node deasserts the bus request signal at least one clock cycle before it send its last set of information, and continues to send information signals in the following clock cycle. By so doing, the node ensures that the extra clock cycle of the bus grant is not wasted.

Method and system for pipelining bus requests

A circuit for translating data in one of a plurality of data formats into data in any of the other of the plurality of the data formats including apparatus for storing data from a first number of input bytes of data, apparatus for selecting unused bytes from the first number of data bytes stored by the apparatus for storing data and from a second number of input bytes of data, apparatus for placing the unused bytes selected in numerical byte order, and apparatus for placing the data in the numerical byte order in byte position for transfer to the format of a destination device.

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Cupertino, CA, United States of America

Charles M Flaig