Maxim Integrated Products, Inc.

Gain Technology Corporation

Charles M Allen

David Bingham

Sui Ping Shieh

Brett J Fox

John M Wettroth

Robert Bruce Denmark

Michael Anthony Ashburn, Jr

Bruce Michael Furman

Robert St Pierre

Michael A Ashburn

A bus interface is provided including a first bus transmission medium adapted for being connected to a control signal source which generates a plurality of sequential control signals. During use, the first bus transmission medium serves to communicate the sequential control signals. Associated with the first bus transmission medium is a second bus transmission medium that is in communication with at least one peripheral device. Such device generates an output signal on the second bus transmission medium upon actuation. Tracking circuitry is connected to the device and remains in communication with the first bus transmission medium. By this interconnection, the tracking circuitry is capable of actuating the device upon the receipt of at least one of the sequential control signals that is associated with the device and is distinguishable by a unique sequential order amongst the remaining sequential control signals.

Two wire mixed signal bi-directional bus interface

The present invention overcomes ISI by precompensating for the anticipated high-frequency energy losses in the transmission media. This precompensation is accomplished using a preemphasis waveform, i.e., driving the differential signal to a value larger than normal on a signal edge. Preemphasis increases the slew rate of edges inside data with a lot of transitions relative to data with fewer transitions, thereby compensating for the low-pass effects of the transmission cable. The present invention further contemplates adaptive control for ensuring that varying operating conditions do not effect preemphasis waveform generation. The first approach involves tracking the operation of a replicate driver for each main driver and adaptively controlling each main driver depending upon feedback from the replicate driver. A second approach, that is both more complicated and more effective, involves measuring the signal and the line impedance at the output of the main driver and adaptively controlling the main driver in response.

Methods and circuits for generating a preemphasis waveform

The present invention enables data communications between multiple devices over a single wire bus. This single-wire interface can be used for sensors, amplifiers, analog-to-digital converters (ADCs), or any other circuit which would normally have an electrical output. Advantages of the present invention include a reduction in device pin count, conservation of the limited number of I/O pins on the control device, and reduced board layout complexity. Speaking generally, each slave device coupled to the single wire bus interface is assigned a different response time window. This enables multiple slave devices to respond to an initial trigger signal generated by the master device without overlapping responses being generated on the single wire bus interface. A suitable slave electrical device includes application circuitry providing state information for the electrical device, an input/output pin suitable for making an electrical coupling external to the electrical device, and a single wire bus interface coupled to the input/output pin and the application circuitry. The single wire bus interface has conversion function circuitry defining a specific response time window for the electronic device. Further, the single wire bus interface is responsive to a start signal received on the input/output pin to generate a response signal within the specific response time window, the response signal indicative of the state information for the electrical device.

Single wire bus interface for multidrop applications

Methods and apparatus for providing network communications capability to a computer system in accordance with standard communication line protocols are described, including interface circuits which sense various characteristics of the communication lines to control or provide signals to control power to line drivers and/or other substantial power consuming circuitry to conserve power when communication line conditions indicate powering such circuits is not useful. Various embodiments are disclosed.

Communication circuit having network connection detection capability

A method and apparatus for customizing the gain of a closed loop operational amplifier during fabrication to a fixed value. The fabricated circuit includes a feedback resistance and a gain resistance coupled to an operational amplifier core. The feedback resistance is set to a preset value by setting links coupled to resistors which make up the feedback resistance.

Fixed gain operational amplifiers

Communication interface circuit having network connection detection

A method and apparatus for providing serial interface capability that detects whether another communications system transmits or receives data on a particular node, and in response, automatically selects to either receive or transmit data on that node. An interface circuit is included that determines whether a particular node is coupled to a receiver circuit or a driver circuit based on the voltage level detected on that node. Based on this determination, the interface circuit is configured to either transmit or receive data on that node. This allows the interface circuit to interact with differently configured communications systems without the need for special cables, or for user intervention.

Method and apparatus for logic network interfacing with automatic

A method and apparatus for transmitting and receiving information over a network that allows the detection of data transmission activity over a wire pair on the network. Within a computer system or other network device a driver-receiver circuit along with an activity detector circuit are coupled to the wire pair such that when the wire pair is inactive, an Inactive signal is asserted, and the activity detector circuit will notify the network device that the network is not currently transmitting data. The activity detector includes a first voltage comparator coupled to a first differential threshold voltage generator and a second voltage comparator coupled to a second differential threshold voltage generator. The absolute value of voltages generated by both differential threshold voltage generators is less than the minimum voltage levels required for a valid signal to be placed on the wire pair, The outputs of the first and second voltage comparators are coupled to an AND gate such that when the voltage differential across the wire pair is not sufficiently high to be a valid logic 1 or a valid logic 0, an Inactive signal is asserted. The Inactive signal, which indicates that the network is not currently transmitting data, is detected by the network device in which the driver-receiver circuit is incorporated.

Method and apparatus for transmitting signals over a wire pair having

A method and apparatus for interfacing a computer system with another system is described including an interface circuit. The interface circuit detects if the voltage level on a signal line represents a valid logic level and if so, provides a valid signal in response. The valid signal allows the computer system to which the interface circuit is coupled to provide power to the interface circuit such that network communication may be established and the interface circuit can internally turn on and off sections of its circuitry without intervention or control by the computer system. In addition, the computer system can use the Invalid signal to control software and/or to notify the user of the status of the computer system. When the interface circuit detects that the voltage level on the signal line does not represent a valid logic level, an Invalid signal is provided allowing the application of power to certain portions of the interface circuit to be suspended so that overall power consumption by the computer system is reduced.

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

Integrated dual charge pump power supply and RS-232 transmitter/receiver

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

Integrated dual charge pump power supply and RS-232-transmitter/receiver

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the conduit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

Growing community of inventors

Sunnyvale, CA, United States of America

Charles M Allen