International Business Machines Corporation

Other

Globalfoundries Inc.

Lenovo (Singapore) Pte. Ltd.

Charles Luther Johnson

Gerald Keith Bartley

Russell Dean Hoover

Steven Paul VanderWiel

Patrick Ronald Varekamp

Robert Russell Williams

Bruce George Rudolph

Joseph Paul Kuczynski

Arvind Kumar Sinha

Paul Allen Ganfield

Kevin Albert Splittstoesser

David R Motschman

Robert F Lembach

John E Kelly, Iii

Timothy Jerome Tofil

Robert K Montoye

James David Strom

Anthony Gus Aipperspach

Jeffrey Haskell Derby

Sheldon Bernard Levenstein

John David Irish

David Howard Allen

David John Krolak

Timothy Hume Heil

Timothy John Mullins

Dheeraj Sreedhar

Dennis T Cox

Leland Leslie Day

Joseph James Cahill

Bruce Ralph Petz

Ronald D Gillingham

Steven D Lewis

David LeRoy Guertin

Mark M Thornton

Mark E Turner

Johnny L Chappell, Jr

John M Ryba

Steven P Vanderwiel

Timothy A Tofil

A fragrance and insect repellant dispenser includes a container, a lid, at least one radial set of dispensing openings, a plurality of top openings, a placement collar, a fan assembly, a power source, a plurality of locking mechanism. The radial set of dispensing openings traverses through a lateral wall of the container. The plurality of top openings traverses through a cover of the lid. The placement collar and the power source are adjacently connected onto the lid. The fan assembly is adjacently connected to the lid, opposite of the placement collar. The fan assembly is electrically connected to the power source and positioned within the container. The lid is perimetrically attached to the container by the plurality of locking mechanisms. Resultantly, the fan assembly is able to dispense at least one solution of fragrance and insect repellant through the plurality of dispensing openings and the plurality of top openings.

Fragrance and insect repellant dispenser

A recliner footrest extension system includes a base-member, and an extension-member. The base-member includes a top-panel, a bottom-panel, and a side-panel in one embodiment. The top-panel, the bottom-panel, and the side-panel are structured and arranged to affix to a recliner footrest by sliding upon the recliner footrest and held upon the footrest by friction. The extension-member is affixed to the base-member by a hinge, with the extension member arranged to support at least one foot of a user when the recliner footrest extension system is in an extended condition.

Recliner footrest extension system and method

A board game that includes a traditional chessboard and two sets of playing pieces, where the playing pieces correspond to that of Western chess, but where each playing piece (possibly save the king) has a top portion and a removable corresponding bottom portion. Each player also is given a second group of top portions that can be interchanged with the original top portions. While game set up and playing piece movement is similar to Western chess, a piece is not 'captured' when an opponent lands on the same board square but 'converted.' The opponent removes the top portion and replaces the piece with a different tone top portion to provide visual indication that the playing piece has been converted to the other side. That converted piece stays on the board instead of being removed with few exceptions. The game ends when one player checkmates the other player's king.

Chess game variant and method of playing the same

In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.

High-performance hash joins using memory with extensive internal parallelism

An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Universal inter-layer interconnect for multi-layer semiconductor stacks

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.

Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip.

Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks

A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

Hybrid bonding techniques for multi-layer semiconductor stacks

A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

Thermal enhancement for multi-layer semiconductor stacks

A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.

A closed circuit rebreather including a breathing hose assembly, head assembly and internal counterlung assembly having axial and radial gas flow passageways therethrough, wherein the assembly is housed within a tank and includes a scrubber substantially enclosed along its longitudinal length within a water impervious counterlung bladder, the scrubber including foraminous inner and outer tubes having a carbon dioxide absorbent material filling the space therebetween.

Closed circuit rebreather

A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip. The components from the 2D chip are layered and coupled to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.

Three dimensional chip fabrication

A first cache simultaneously broadcasts, in a single message, a request for a cache line and a request to accept a future related evicted cache line to multiple other caches. Each of the multiple other caches evaluate their occupancy to derive an occupancy value that reflects their ability to accept the future related evicted cache line. In response to receiving a requested cache line, the first cache evicts the related evicted cache line to the cache with the highest occupancy value.

Intelligent cache injection

A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

SRAM that can be clocked on either clock phase

Growing community of inventors

Rochester, MN, United States of America

Charles Luther Johnson