Chartered Semiconductor Manufacturing Ltd (corporation)

Advanced Power Devices, Inc.

Aptos Corporation

Apd Semiconductor, Inc.

Charles Lin

Lup San Leong

Feng Chen

Yih-Shung Lin

Vladimir Rodov

Geeng-Chuan Chern

Paul C Chang

Wayne Y W Hsueh

Erzhuang Liu

Huang Liu

Jia Zhen Zheng

John Leonard Sudijono

Yi Liang Xu

Chung Woh Lai

Eng Hua Lim

Beichao Zhang

Ser Wee Quek

Arthur Ang

Ching-Lang Chiang

Jimmy Lo Yuk Ting

Ser Wee Sebastian Quek

Quah Ya Lin

Jane C M Hui

Yih Shung Lin

Xiaosong Tang

Erzhuang Lzu

Jimmy Lo(Yuk Ting)

Liu Erzhuang

Hai Jiang Peng

In one embodiment, a dielectric layer () overlying a semiconductor substrate () is uniformly polished. During polishing, the perimeter () of the semiconductor substrate () overlies a peripheral region () of a polishing pad () and an edge portion () of the front surface of semiconductor substrate () is not in contact with the front surface () of the polishing pad (), in the peripheral region (). As a result, the polishing rate at the edge portion () of the semiconductor substrate () is reduced, and the semiconductor substrate () is polished with improved center to edge uniformity. Since the semiconductor substrate () is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion () of the semiconductor substrate () are not over polished.

Polishing apparatus and method for forming an integrated circuit

In one embodiment, a semiconductor substrate () is uniformly polished using a polishing pad () that has a first polishing region (), a second polishing region (), and a third polishing region (). The semiconductor substrate () is aligned to the polishing pad (), such that the center of the semiconductor substrate () overlies the second polishing region (), and the edge of the semiconductor substrate overlies the first polishing region () and the third polishing region (). During polishing, the semiconductor substrate () is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate (). This allows the semiconductor substrate () to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate () are not over polished.

A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.

Method of making an ultimate low dielectric device

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Method of fabricating power rectifier device to vary operating parameters and resulting device

A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Method of cobalt silicidation using an oxide-Titanium interlayer

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region

A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titanium layer, where the titanium layer contacts the electrode contact region of the silicon substrate layer. There is then processed thermally the titanium layer in a nitrogen containing atmosphere to form a titanium silicide layer in contact with the electrode contact region and a titanium nitride layer formed thereover, where the titanium layer is completely consumed in forming the titanium silicide layer and the titanium nitride layer. Finally, there is formed upon the titanium nitride layer a barrier layer.

Titanium nitride/titanium tungsten alloy composite barrier layer for integrated circuits

In one embodiment, a semiconductor substrate ( ) is uniformly polished using a polishing pad ( ) that has a first polishing region ( ), a second polishing region ( ), and a third polishing region ( ). The semiconductor substrate ( ) is aligned to the polishing pad ( ), such that the center of the semiconductor substrate ( ) overlies the second polishing region ( ), and the edge of the semiconductor substrate overlies the first polishing region ( ) and the third polishing region ( ). During polishing, the semiconductor substrate ( ) is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate ( ). This allows the semiconductor substrate ( ) to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate ( ) are not over polished.

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Method of fabricating power rectifier device

In one embodiment, a dielectric layer ( ) overlying a semiconductor substrate ( ) is uniformly polished. During polishing, the perimeter ( ) of the semiconductor substrate ( ) overlies a peripheral region ( ) of a polishing pad ( ) and an edge portion ( ) of the front surface of semiconductor substrate ( ) is not in contact with the front surface ( ) of the polishing pad ( ), in the peripheral region ( ). As a result, the polishing rate at the edge portion ( ) of the semiconductor substrate ( ) is reduced, and the semiconductor substrate ( ) is polished with improved center to edge uniformity. Since the semiconductor substrate ( ) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion ( ) of the semiconductor substrate ( ) are not over polished.

An improved and new substrate carrier head for use in a CMP apparatus is described. The new substrate carrier head has a substrate retaining ring with embedded intersecting channels in the outer face. The embedded intersecting channels improve the circulation of polishing slurry to and from the polished substrate and polishing byproducts away from the polished substrate and thereby improve the polishing uniformity on the substrate.

Chemical mechanical polishing apparatus improved substrate carrier head and method of use

A method for depositing silicon dioxide between features has been achieved. The method may be applied intermetal dielectrics, interlevel dielectric, or shallow trench isolations. This method prevents dielectric voids, corner clipping, and plasma induced damage in very small feature applications. Features, such as conductive traces, are provided overlying a semiconductor substrate where the spaces between the features form gaps. A silicon dioxide liner layer is deposited overlying the features and lining the gaps, yet leaving the gaps open. The silicon dioxide liner layer depositing step is by high density plasma, chemical vapor deposition (HDP CVD) using a gas mixture comprising silane, oxygen, and argon. The argon gas pressure, chamber pressure, and the sputter rf energy are kept low. A silicon dioxide gap filling layer is deposited overlying the silicon dioxide liner layer to fill the gaps, and the integrated circuit device is completed. The silicon dioxide gap filling layer depositing step is by high density plasma, chemical vapor deposition (HDP CVD) using a gas mixture comprising silane, oxygen, and argon. The argon gas pressure and chamber pressure are kept low while the sputter rf energy is increased.

Two-step, low argon, HDP CVD oxide deposition process

It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing methods for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered &ldquo;hard mask&rdquo; on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal. A double coating scheme of low dielectric constant insulators are used in this application. The third embodiment uses a hard mask stack over the interconnect metal lines, with a silicon oxynitride DARC costing on top of metal, and an adhesion layer between the low dielectric material and the top dielectric layer.

Gap filling process in integrated circuits using low dielectric constant materials

A wafer chuck for positioning and releasably holding a wafer includes a support platform having an upper surface for positioning and supporting the wafer. Wafer banking pins are affixed to the support platform for positioning the wafer. A lift device acting on the wafer when it rests on the support platform to move the wafer relative to the support platform in a slanted direction away from the support platform and wafer banking pins. The lift device has a plurality of wafer lifting fingers that cooperatively extend in a biased and substantially vertical direction are disposed in a pattern to be supportive of the wafer. Each of the wafer lifting fingers has an end portion that is movable relative to the support platform between a first position at which it is retracted from the upper surface of the support platform and a second position at which it protrudes from the upper surface of the support platform so as to engage the wafer to lift it relative to the support platform.

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Singapore, Singapore

Charles Lin