International Business Machines Corporation

Globalfoundries Inc.

Ancosys Gmbh

Elpis Technologies Inc.

Globalfounries Inc.

Charles Leon Arvin

Christopher David Muzzy

Wolfgang Sauter

Brian Michael Erwin

Brian W Quinlan

Thomas Weiss

Jeffrey P Gambino

Harry David Cox

Eric D Perfecto

Thomas Anthony Wassick

Krystyna Waleria Semkow

Michael S Gordon

Raschid Jose Bezama

Mark William Kapfhammer

Charles L Reynolds

Bhupender Singh

Brian Richard Sundlof

Glen Nelson Biggs

Tracy A Tong

Phillip W Palmatier

Freddie Torres

Joseph C Sorbello

Krishna R Tunga

Timothy Harrison Daubenspeck

Chris Muzzy

Hariklia Deligianni

Timothy Dooling Sullivan

Jean Audet

Steve Ostrander

Jon Alfred Casey

Shidong Li

Steven Paul Ostrander

Jennifer D Schuler

Lawrence Alfred Clevenger

Joshua M Rubin

David John Russell

Richard Francis Indyk

Gary William Maier

Hsichang Liu

Karen P McLaughlin

Clement J Fortin

Kamal Kumar Sikka

Minhua Lu

Thomas Edward Lombardi

David Michael Audette

Grant W Wagner

Srinivasa S N Reddy

Charles F Musante

Sylvain Pharand

Kevin Drummond

Jürg Stahl

Arvind Kumar

Robert K Leidy

Gareth Geoffrey Hougham

Thomas J Brunschwiler

David L Questad

Kamalesh K Srivastava

Peter Jeffrey Brofman

Kenneth Charles Marston

Donald W Henderson

Dinesh Gupta

Glenn A Pomerantz

Julien Sylvestre

Arthur Gilman Merryman

Renee L Weisman

Dennis R Conti

Francesco Preda

Marcus E Interrante

George John Scott

Alexandre Blander

Maryse Cournoyer

Jorge A Lubguban

Valérie Anne Oberson

Hai Pham Longworth

Luca Del Carro

Levi A Campbell

Alfred Grill

Mark Kenneth Hoffmeyer

Hilton T Toy

Prabjit Singh

Benjamin V Fasano

Sushumna Iruvanti

Sung Kwon Kang

Steven Lorenz Wright

Mario John Interrante

Sarah Huffsmith Knickerbocker

Luc Gilbert Guerin

Daniel George Berger

Tuhin Sinha

Sylvain E Ouimet

Charles C Goldsmith

Valerie A Oberson

Srinivasa N Reddy

Mark S Chace

Richard A Shelleman

Franklin M Baez

John R Pennacchia

Qin Yuan

Carla A Bailey

Janine L Protzman

A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Electronic package with varying interconnects

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

High bandwidth module

An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Near tier decoupling capacitors

A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Spacer for die-to-die communication in an integrated circuit and method for fabricating the same

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

Polygon integrated circuit (IC) packaging

An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Direct attachment of capacitors to flip chip dies

An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.

Alignment carrier for interconnect bridge assembly

A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Thin film capacitors for core and adjacent build up layers

An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

Enlarged conductive pad structures for enhanced chip bond assembly yield

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Mixed UBM and mixed pitch on a single die

A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

Mitigating thermal-mechanical strain and warpage of an organic laminate substrate

Disclosed are embodiments of forming porous copper on the end of a copper pillar. The embodiments may be used to remove solder from selected locations on a chip or laminate substrate.

Personalized copper block for selective solder removal

A deionized-water cooling system for electrical equipment is provided. The system includes a cooling loop in which water comes into contact with the electrical equipment and a deionization bypass connected to the cooling loop. The deionization bypass includes a first filter component configured to remove dissolved oxygen, a second filter component configured to filter solid particles, a deionization cartridge configured to deionize water, and a plurality of valves configured to control a water flow within the deionization bypass.

Deionized-water cooling for electrical equipment

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Direct bonded heterogeneous integration packaging structures

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Poughkeepsie, NY, United States of America

Charles Leon Arvin