International Business Machines Corporation

Charles L Standley

Geraldine C Schwartz

Joseph S Logan

William L Guthrie

John L Mauer, Iv

William J Patrick

Laura B Rothman

Kathleen A Perry

John Edward Cronin

Klaus D Beyer

Jacob Riseman

Carter W Kaanta

Barbara Jean Luther

William A Pliskin

Paul M Schaible

Jimmie L Powell

Stanley R Makarewicz

Eric Mendel

John Suierveld

Melanie M Chow

Albert P Lee

George S Gati

A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier. In a second example a substrate having a patterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.

Chem-mech polishing method for producing coplanar metal/insulator films

Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

Method for producing coplanar multi-level metal/insulator films on a

A composite insulator structure separating adjacent layers of patterned metal on an LSI chip is disclosed. The bottom layer of sputtered oxide is thicker than the top layer and is preferably planarized. The top layer is conformal plasma nitride so as to uncover unwanted projections on the underlying metal and prevent interlevel shorting between the patterned layers.

Composite insulator structure

Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

Planar multi-level metal process with built-in etch stop

A process is disclosed for etching openings in a relatively thick layer of borosilicate glass while controlling the degree of taper of the sidewalls of the opening, the taper being in excess of about 45.degree.. The process involves (1) depositing a layer of silicon nitride that contains silicon in an amount in excess of stoichoimetric in Si.sub.3 N.sub.4, (2) densifying the silicon nitride layer, (3) depositing a layer of resist, (4) exposing and developing the layer of resist to define a desired pattern of openings in the borosilicate glass layer, (5) removing the exposed silicon nitride areas, and (6) subjecting the resultant exposed borosilicate glass surface to an etchant for the glass.

Process for the controlled etching of tapered vias in borosilicate glass

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Wappingers Falls, NY, United States of America

Charles L Standley