International Business Machines Corporation

Charles L Meiley

Richard LaVerne Malm

Gustavo Enrique Tellez

Philip S Honsinger

Reginald B Wilcox, Jr

Steven G Lovejoy

Gary R Doyle

Gorden S Starkey

Frank Albert Nemec, Ii

A method for automatically wiring (i.e., routing) an integrated circuit chip after completing the placement of cells on the chip is described. The method employs a maze routing such that the spacing between the routed wires is increased, while at the same time maintaining control over the total wiring length. The maze routing herein described is modified to improve chip yield, reduce wiring capacitance, limit power consumption and coupled signal noise, all of which are achieved by increasing wire-to-wire spacings.

Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing

A method and apparatus for solving grid point layouts using massively parallel computers to solve each wiring connection or grid point independently. By leaving the solution in a global perspective, and solving the problem using fine grain parallelism, wiring solutions and optimized layouts are achieved in a shorter amount of time.

Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm

A computer-implementable method for wiring congested areas in a VLSI design detects overflows indicating an area of congestion in the VLSI design and defines a bounding area around the area of congestion. Attachment points are created at locations where wires cross the bounding area and the entire bounding area, with the attachment points, is extracted from the VLSI design as a sub-design. Initial wire weights are assigned to wiring parameters associated with the sub-design. Thereafter, an iterative process is commenced to derive a wiring solution for the sub-design. In a first step of the iterative process, an attempt is made to wire the sub-design with the assigned wire weights. In subsequent steps, at least one wire weight is changed and a new attempt is made to wire the sub-design using the new wire weight values. The process continues in this manner until a wiring attempt completes successfully. The wired solution for the sub-design is then placed back into the VLSI design.

Sub-problem extraction method for wiring localized congestion areas in

An improved technique for processing large amounts of information and displaying that information graphically. The graphic display focuses attention to suspect areas employing colors and shading techniques to quickly focus the user's attention to problem areas. Multidimensional objects clearly convey global information concerning circuits employing millions of networks of electrical characteristics.

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San Jose, CA, United States of America

Charles L Meiley