Micron Technology Incorporated

Nan Ya Technology Corporation

Micron Semiconductor, Inc.

Charles L Ingalls

Scott James Derner

Howard Kirsch

Tae Hyoung Kim

Christopher John Kawamura

Huy Thanh Vo

David L Pinney

Fernando N Gonzalez

Sei Seung Yoon

Graham Richard Wolstenholme

Mark R Thomann

Raymond A Turi

Toby D Robbs

K Shawn Smith

Jeremy J Gum

Gurtej S Sandhu

Werner Juengling

Hiroki Fujisawa

Jeffrey P Wright

Richard Edward Fackenthal

Michael Amiel Shore

Richard J Hill

Shigeki Tomishima

Christopher K Morzano

Victor Wong

Kim M Pierce

J Wayne Thompson

Steve V Cole

Stephen D Holland

Richard A Mecier

Todd A Merritt

Timothy B Cowles

George B Raad

Jiyun Li

Zhong-Yi Xia

Jonathan T Doebler

Fredrick David Fishburn

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

Storing memory array operational information in non-volatile subarrays

Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

Integrated memory comprising secondary access devices between digit lines and primary access devices

Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors

A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

Pre-sense gut node amplification in sense amplifier

Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

Apparatuses and methods for sense line architectures for semiconductor memories

A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

FX driver circuit

Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

Array data bit inversion

Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region gatedly coupled with a second source/drain region. A digit line is coupled with the first source/drain region. A charge-storage device is coupled with the second source/drain region through an interconnect. The interconnect includes a length of a semiconductor material. A protective transistor gates a portion of the length of the semiconductor material.

Integrated memory comprising gated regions between charge-storage devices and access devices

In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

Memory arrays with vertical thin film transistors coupled between digit lines

Embodiments herein relate to column select circuitry of a memory device. Specifically, the column select circuitry includes a pre-header circuit coupled to a pre-driver circuit. The pre-header circuit is configured to couple a gate of a transistor of a main column select driver circuit of the column select circuitry to a first voltage supply during operation and a second voltage supply when in a standby state. A voltage of the second voltage supply is greater than a voltage of the first voltage supply. The voltage of the second power supply applied to the gate of the transistor of the main column select driver circuit reduces current leakage through the transistor and enables a reduction in a size of the column select circuitry.

Driver leakage control

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

Half density ferroelectric memory and operation

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Meridian, ID, United States of America

Charles L Ingalls