Research Triangle Institute

Mcnc

Charles Kenneth Williams

Christopher Andrew Bower

Mark Windsor Roberson

Philip E Garrou

Philip A Deane

Arnold Reisman

Dorota Temple

Mark D Kellam

Dean Michael Malta

Nandini Tandon

A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.

Three dimensional interconnect structure and method thereof

A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.

Structure and process for electrical interconnect and thermal management

A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element. The method supplies a fluid through the entrance through-hole, flows the fluid through the coolant channel between the first substrate and second substrates, and removes the fluid from the coolant channel through the exit through-hole.

Three dimensional electronic and optical coupling devices that are capable of providing high speed coupling over a large frequency range while limiting the amount of space consumption in the communications network. An optical or electrical coupling device comprises a first substrate and a second substrate adjacent to the first substrate having one or more optical waveguides or microstrips formed thereon. The substrates will have disposed thereon conductive microstrips and/or dielectric elements. The one or more optical waveguides or microstrips formed on the first substrate correspond to at least one optical waveguides or microstrips formed on the second substrate so as to facilitate optical coupling between the corresponding waveguides. Precise spacing between the substrates and precise spacing between the optical waveguides or microstrips facilitate the requisite optical/RF coupling.

Three dimensional multimode and optical coupling devices

A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without 'bird's beak' formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.

Growing community of inventors

Raleigh, NC, United States of America

Charles Kenneth Williams