Micron Technology Incorporated

Charles K Snodgrass

John R Tuttle

Robert R Rotzoll

George Edward Pax

David Howard Allen

Robert L Totorica

Charles S Alexander

David A Reichle

Fremont S Smith

Bruce A Dickey

Armando Montalvo

Paul A LaBerge

Jeffrey Jay Rooney

Phillip A Rasmussen

An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.

Sub-instruction repeats for algorithmic pattern generators

Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

Integrated testing apparatus, systems, and methods

A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits. Write data is generated based on a subset of the modified address bits.

Microsequencer with nested loop counters

A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port. As a result, many integrated circuits under test may share the first signal port through the failure processor, because the integrated circuits under test are not providing output data on the first signal port to an external test data evaluation apparatus. The efficiency with which integrated circuits may be tested is thereby increased.

On-board testing circuit and method for improving testing of integrated circuits

Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Circuitry for and system and substrate with circuitry for aligning output signals in massively parallel testers and other electronic devices

Signal alignment circuitry aligns (i e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock. To control the rising and falling edges of one of the test signals, and thereby align the signal with the other test signals, the control circuitry first sweeps the delay in the rising edge and falling edge delay elements until the latched-in signal transitions. Then, the reference clock is delayed by a known amount of time, and the delay in the rising edge and falling edge delay elements is again swept until the latched-in signal transitions. This provides enough information to characterize delay functions of the rising edges and falling edges of the signal in terms of a point-slope formula, which, in turn, allows for complete control over the rising and falling edges of the signal and for the alignment of the signal with the other signals.

System and method for aligning output signals in massively parallel testers and other electronic devices

Programmable pattern generator

Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the flux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock. To control the rising and falling edges of one of the test signals, and thereby align the signal with the other test signals, the control circuitry first sweeps the delay in the rising edge and falling edge delay elements until the latched-in signal transitions. Then, the reference clock is delayed by a known amount of time, and the delay in the rising edge and falling edge delay elements is again swept until the latched-in signal transitions. This provides enough information to characterize delay functions of the rising edges and falling edges of the signal in terms of a point-slope formula, which, in turn, allows for complete control over the rising and falling edges of the signal and for the alignment of the signal with the other signals.

System and method for aligning output signals in massively parallel

A method for reducing the dynamic range required of an automatic gain control (AGC) circuit in a remote transceiver in 2-way communication between local and remote transceivers. By repeatedly transmitting a signal with successively increasing power from one transceiver until a response is received from the other transceiver, the dynamic range and hence complexity of the receiving circuit may be greatly reduced. The operating power of the remote transmitter can then be adjusted according to the level used by the local transmitter, thereby promoting the efficent use of the remote's power supply.

Methods and systems for gain adjustment in two-way communication systems

The present invention provides for a method and an apparatus for routing electrical signals. The method includes accessing a plurality of electrical circuits. The apparatus includes a supervisory circuit capable of delivering two access signals from a group of first, second, third, and fourth access signals, wherein the supervisory circuit is capable of delivering one of the first and third access signals, and one of the second and fourth access signals. A plurality of electrical circuits is organized into first and second rows. A first portion of the plurality of electrical circuits in the first and second rows, is coupled to a first access signal line. A second portion of the plurality of electrical circuits in the first and second rows is coupled to a second access signal line. The first and second portions of the plurality of electrical circuits in said first row are coupled to a third access signal. The first and second portions of said plurality of electrical circuits in the second row are coupled to a fourth access signal. An access signal is delivered on one of the first and third access signal lines and on one of the second and fourth access signal lines, the electrical circuits being accessed in response to receiving two access signals.

Method and apparatus for signal routing to achieve signal-efficiency

A method and system that uses an anticipatory signal to pre-adjust the output of the power supply to compensate for an upcoming load change, thereby minimizing the voltage deviation at the load. A control circuit, such as a processor, controlling the system generates an anticipatory signal indicating an upcoming change in the load that is input to the power supply. The power supply, in response to the signal from the processor, adjusts the output of the power supply accordingly to compensate for the upcoming load change. When the system performs the operation that results in the load change, the power supply output has already been adjusted accordingly and the deviation of the load voltage caused by the change in the load is minimized.

System with anticipatory power supply load signal

One or more interrogating commander stations and an unknown plurality of responding responder stations coordinate use of a common communication medium. Each commander station and each responder station is equipped to broadcast messages and to check for error in received messages. When more than one station attempts to broadcast simultaneously, an erroneous message is received and communication is interrupted. To establish uninterrupted communication, a commander station broadcasts a command causing each responder station of a potentially large first number of responder stations to each select a random number from a known range and retain it as its arbitration number. After receipt of such a command, each addressed responder station transmits a response message containing its arbitration number. Zero, one, or several responses may occur simultaneously. By broadcasting requests for identification to various subsets of the full range of arbitration numbers and checking for an immediate error-free response, a commander station can determine the arbitration number of every responder station capable of communicating at the time. Consequently, a commander station can conduct subsequent uninterrupted communication with each responder station, for example by addressing only one responder station. Responder stations of this invention -require minimal logic and circuitry to respond to multiple commander stations.

Data communication system using indentification protocol

A method for reducing the dynamic range required of a receiver circuit in a remote transceiver in 2-way communication between local and remote transceivers. By repeatedly transmitting a signal with successively increasing power from one transceiver until a response is received from the other transceiver, the dynamic range and hence complexity of the receiving circuit may be greatly reduced. The operating power of the remote transmitter can then be adjusted according to the level used by the local transmitter, thereby promoting the efficent use of the remote's power supply.

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Boise, ID, United States of America

Charles K Snodgrass