Socionext Inc.

Charles Joseph Dedic

Niklas Linkewitsch

Guido Dröge

Ian Juso Dedic

Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Processing circuitry comprising a current-compensation unit

The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.

Analogue-to-digital converter circuitry comprising capacitive successive-approximation control circuitry

The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

Semiconductor integrated circuitry

Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

Clock distribution

A non-linearity evaluation circuit for use with a signal generator having at least a partly non-linear operation. The non-linearity evaluation circuit may include a detection unit operable to detect a given amplitude attribute in a target signal generated by the signal generator, a time position of the amplitude attribute in the target signal defining a time location of a snapshot time window relative to the target signal, a part of the target signal occupying the snapshot time window being a corresponding signal snapshot, and a presence of the given amplitude attribute indicating that the signal snapshot includes noise due to the non-linear operation of the signal generator. The non-linearity evaluation circuit may further include a controller operable to analyse the signal snapshot rather than a larger part of the target signal and to evaluate the non-linear characteristics of the operation of the signal generator based on the analysis.

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London, United Kingdom

Charles Joseph Dedic