Siemens Energy & Automation, Inc.

Siemens Energy & Automotive, Inc.

Charles Johnson

Ronald B Harris

Alan Weddle

Michael Hales

Certain exemplary embodiments can comprise a method for detecting a circuit fault, comprising: for a sensor coupleable to an input circuit, the sensor characterized by an output signal operating voltage range: automatically causing the sensor to be electrically disconnected from the input circuit; automatically causing an invalid sensor voltage to be applied to the input circuit, the invalid sensor voltage having a value outside the output signal operating voltage range for the sensor; automatically causing the invalid sensor voltage to be removed from the input circuit; automatically causing the sensor to be electrically connected to the input circuit; and, in the event that an input circuit voltage value is outside the output signal operating voltage range for the sensor, automatically providing notification that a circuit fault is associated with the sensor.

Systems, methods, and devices for detecting circuit faults

As provided, a system and method for automatically correcting timers to improve timing accuracy. The system and method provides for the use of inexpensive low tolerance resonators or oscillators that meet the internal timing specifications of applications of isochronous I/O over Profibus. Accordingly, the specified error rate (jitter) to appropriately maintain I/O is met efficiently and at low cost.

System and method for automatically correcting timers

A parallel processor with a built-in sub-phase clocking scheme is provided to execute sequentially executed programmable logic controller (PLC) programs in a parallel method. A translator program will translate the PLC logic design from a coding language into Electronic Design Interchange Format and that will be eventually converted to a hardware or software embodiment of the logic. The processor provides a plurality of sub-phase clock periods. The translator assigns to the same sub-phase period program elements that process their tasks in the same range of time. The elements are grouped into sub-phase so that logic elements are performed lock-step to ensure that downstream element are performed at a time when they have valid values at their inputs. The processor consequently avoids race conditions in the system and allows the parallel execution speedup of programs written for a sequential machine such as a PLC.

Programmable controller with sub-phase clocking scheme

At least one exemplary embodiment of the present invention includes a method for compensating for delays in a circuit of a serial encoder. The method includes determining at least one delay associated with the circuit of the serial encoder. The method also includes adjusting an internal clock signal received by a data receiving memory associated with the serial encoder to account for the at least one determined delay.

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Gray, TN, United States of America

Charles Johnson