Rambus Inc.

Cadence Design Systems, Inc.

Charles J Wilson

Larry Arbuthnot

Sreeja Menon

Sudhir Kumar Katla Shetty

Michael Thomas Imel

Nikhil Raghavendra Rao

A memory controller includes a request queue and associated logic for efficiently managing the request queue based on various timing constraints of the memory device. A single request queue for the memory device stores read and write requests spanning different banks of the memory device. In each memory controller cycle, selection logic may select both a row request and a column request (relating to a different bank than the row request) for issuing to the memory device based on a set of timing status bits. Following issuance of requests, the memory controller updates the queue to maintain the queued requests in a time-ordered, compressed sequence. The memory controller furthermore updates the timing status bits that are used by the selection logic to select requests from the queue based on a history of past memory requests.

Reordering memory controller

System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these 'mapped' connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.

Memory interface mapping

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Portland, OR, United States of America

Charles J Wilson