Motorola Corporation

Charles J Varker

Syd R Wilson

Richard B Gregory

Michael L Dreyer

Thomas E Zirkle

Wayne M Paulson

H Ming Liaw

Ganesh Rajagopalan

Marie E Burnham

In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow. In a second approach, an interconnect level (50) is formed of a polycrystalline material and connects two points in the semiconductor device using essentially only a plurality of branches (52) each having a linewidth (W) less than the median grain size of the polycrystalline material. In a third approach, an interconnect run (60) consists essentially of a plurality of upper and lower straps (62, 64) connected by a plurality of interlevel connectors (66) so that a chain is provided which connects substantially the full length between two points in the semiconductor device.

Interconnect run between a first point and a second point in a

A method and an electrically conductive interconnect structure (30) for controlling electromigration. The electrically conductive interconnect structure (30) comprises a groove (33) adjacent an electrically conductive interconnect (39). The electrically conductive interconnect (39) is patterned from a deposited layer of conductive material which contains global grain microstructures. Moreover, the electrically conductive interconnect (39) is patterned to have polycrystalline and single-grain segment lengths that are less than a length at which an electromigration flux fails to overcome a gradient-driven counter flux in a line segment. The groove (33) controls the polycrystalline and single-grain segment lengths to be less than the critical length, thereby reducing electromigration.

Method for controlling electromigration and electrically conductive

In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow. In a second approach, an interconnect level (50) is formed of a polycrystalline material and connects two points in the semiconductor device using essentially only a plurality of branches (52) each having a linewidth (W) less than the median grain size of the polycrystalline material. In a third approach, an interconnect run (60) consists essentially of a plurality of upper and lower straps (62,64) connected by a plurality of interlevel connectors (66) so that a chain is provided which connects substantially the full length between two points in the semiconductor device.

Semiconductor device interconnect layout structure for reducing

A means and method is described for shielding semiconductor charge storage devices from the effects of particles or ionizing radiation absorbed within the bulk of the semiconductor substrate, by providing a free carrier shield consisting of a buried layer of very low lifetime in the undisturbed material below the depletion regions associated with the charge storage devices. The very low lifetime layer is obtained by ion implantation of a super-saturated zone of impurities such as oxygen which provide deep recombination centers and which react chemically with the substrate material so as to provide thermally stable complexes which do not anneal away during post implant heating cycles. Concentrations of lifetime killing impurities significantly exceeding the solid solubility limit are achieved so that the lifetime reduction in the carrier shield region greatly exceeds that obtainable by prior art methods. Partial shielding is also provided against carriers injected by nearby junctions or introduced by charge pumping during circuit operation.

Charge storage depletion region discharge protection

Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10.sup.15 ions/cm.sup.2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The effects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where it precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

Means for stabilizing polycrystalline semiconductor layers

Hillock formation as a result of heating uncapped polycrystalline silicon layers can be avoided by first implanting the uncapped poly layers with silicon, oxygen, or nitrogen prior to heating. Equivalent mono-atomic oxygen or nitrogen doses in the range of about 10.sup.15 to about 5.times.10.sup.16 ions/cm.sup.2 at energies in the range 10-50 keV are useful with good results being obtained with equivalent oxygen doses of 2.times.10.sup.15 ions/cm.sup.2 at 30 keV. When polysilicon layers with this oxygen implant are heated to about 1150 degrees C., a temperature which would ordinarily produce pronounced hillock formation in un-capped, un-treated poly layers, it is found that hillock formation is suppressed. The implanted oxygen concentrations are far below what is required to produce a separate oxide layer or phase. Some effect on poly layer sheet resistance is observed for implanted oxygen but the implanted layers have sheet resistances within a factor of two of those without the oxygen implants.

Method of preventing hillock formation in polysilicon layer by oxygen

A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively placing of a metal dopant in a region of the device or circuit. This aids in increasing the manufacturing yields of the switching device, and increases the number of active traps for minority carriers.

Metal redistribution by rapid thermal processing

MOS transistors in which the source and drain contact are isolated from the common substrate are formed by using the gate conductor to mask a high dose high energy implant which creates a thin dielectric region within the body of the common substrate beneath the source and drain regions, but not beneath the channel region. For single crystal silicon substrates, oxygen and nitrogen are the preferred ions for use in forming the buried dielectric region. The conductive gate must be sufficiently thick so as to preclude the implanted oxygen or nitrogen ions from reaching the underlying gate dielectric or the portion of and channel region of the device will be substantially free the substrate beneath the gate. This ensures that the gate and channel region of the device will be substantially free of the implant damage which otherwise occurs during formation of the buried dielectric regions. Dielectric isolation walls are conveniently provided laterally exterior to the source-drain regions. The source-drain and gate regions are self-aligned to each other. Typical oxygen implant doses to form the buried dielectric layer are 1.7.-2.2.times.10.sup.18 ions/cm.sup.2 at an energy of about 150 KeV.

Forming depthwise isolation by selective oxygen/nitrogen deep implant

Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10.sup.15 ions/cm.sup.2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The efffects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where is precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

Means and method for stabilizing polycrystalline semiconductor layers

A combined method for purifying silicon and growing single crystals. A multiple step process is disclosed by which metallurgical grade silicon is purified and converted into a high quality monocrystalline silicon ingot. Each of the steps in the process is designed to remove specific impurities and thus improve the electrical quality of the silicon material. First, the insoluble slag and high segregation coefficient impurities are removed. Soluble impurities are then removed by a reactive gas step, and by a liquid-liquid extraction step using reactive metallic oxides or an oxide solvent. The remaining impurities are removed by segregation during freezing by pulling an ingot from a portion of the molten metallurgical grade silicon. The ingot so formed is then used to charge a second crystal puller. One or more of the previous purifying steps can then be repeated for the charge of the second crystal puller and an ingot of improved purity can be pulled from the melt of the second puller. In like manner, third and successive reiterations of the process can be used to obtain silicon of the desired purity and crystal quality.

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Scottsdale, AZ, United States of America

Charles J Varker