Intel Corporation

University of California

Charles Henry Wallace

Paul Anton Nyhus

Swaminathan Sivakumar

Leonard P Guler

Tahir Ghani

Mohit K Haran

Elliot Tan

Manish Chandhok

Richard E Schenker

Oleg Golonzka

Florian Gstrein

Eungnak Han

Robert L Bristol

Gurpreet Singh

Curtis W Ward

Kevin Lai Lin

Ruth Amy Brain

Marie Krysak

David N Shykind

James M Blackwell

Chanaka D Munasinghe

Richard Barry Kaner

Andy Chih-Hung Wei

Michael Harper

Noriyuki Sato

Mauro J Kobrinsky

Rami Hourani

Nadia M Rahhal-Orabi

Nafees Kabir

Jason W Klaus

Shem Ogadhoh

Zhanping Chen

Biswajeet Guha

Elijah V Karpov

Bernhard Sell

Hui Jae Yoo

William Hsu

Yan A Borodovsky

Andrew W Yeoh

Urusa Alaan

Gopinath Bhimarasetti

Stephanie A Bojarski

Reken Patel

Robert M Bigwood

Marvin Young Paik

Hossam A Abdallah

Matthew L Tingey

Sukru Yemenicioglu

Deepak S Rao

Alexander F Kaplan

Krishna Kumar Ganesan

James Jeong

Shannon Daviess

Sean Michael Pursel

Debashish Basu

Jinnie Aloysius

Hyunsoo Park

Mohammad Hasan

Chul-Hyun Lim

Makram Abd El Qader

Nityan Labros Nair

Seungdo An

Xuanxuan Chen

Brandon Jay Holybee

Tsuan-Chung Chang

Fitih M Cinnor

Gobind Bisht

Jonathan Laib

Daniel James Bahr

Kilhyun Bang

Suzanne S Rich

Pratik A Patel

Allen B Gardiner

Sudipto Naskar

Jennifer O'Loughlin

Guillaume Bouche

Sam Sivakumar

Zheng Guo

Chi-Hwa Tsang

Ryan Pearman

Saurabh Morarka

Clifford L Ong

Sang Hun Lee

Aravind S Killampalli

Uddalak Bhattacharya

Marni Nabors

Nikhil Mehta

Martin Weiss

Tayseer Mahdi

Todd R Younkin

Seongtae Jeong

Conor P Puls

Smita Shridharan

Sven Eric Henrichs

Changyok Park

Shakul Tandon

Swaminathan (Sam) Sivakumar

Hyuk Ju Ryu

Arvind Sundaramurthy

William T Blanton

Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.

Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner

Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.

Integrated circuit structures having dielectric anchor void

Techniques are provided herein to form an integrated circuit having gate cut structures or plug structures between source or drain regions, with an angled cut made to the top portion of the structures. In an example, a semiconductor device includes a semiconductor region extending between source and drain regions, and a gate structure extending over the semiconductor region. A gate cut structure is present adjacent to the semiconductor device and interrupts the gate structure. The gate cut structure has a first width along a first plane that extends through the semiconductor region and a second width along a second plane parallel to the first plane and above the semiconductor region, where the first width is greater than the second width. Similar angled plug structures may be provided adjacent to the source and drain regions to increase the landing area made to the metal contacts on the source and drain regions.

Angled gate or diffusion plugs

Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.

Topside plugs for epitaxial contact formation

Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication

Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Integrated circuit structure with recessed self-aligned deep boundary via

A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

Integrated circuit structures having maximized channel sizing

Techniques are provided herein to form semiconductor devices having different pitches, yet maintaining a substantially similar depth to the diffusion regions between the semiconductor regions. In an example, a row of semiconductor devices having semiconductor regions extending in a first direction can include some devices having a diffusion region with a first width in the first direction and some devices having a diffusion region with a second width in the first direction, where the second width is different from the first width. The depths of the diffusion regions having both the first and second widths may be substantially similar (e.g., within 2 nm or less of one another). In some examples, the bottom surface of at least one of the wider diffusion regions has a step profile.

Deep etch processing for transistors having varying pitch

Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.

Backside electrical contact for PMOS epitaxial voltage supply

Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

Integrated circuit structures having backside gate tie-down

Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.

Extreme ultraviolet lithography patterning with assist features

Integrated circuit structures having backside gate cut or backside trench contact cut, and methods of fabricating integrated circuit structures having backside gate cut or backside trench contact cut, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first gate electrode is around the first stack of nanowires. A second gate electrode is around the second stack of nanowires. A dielectric structure is between the first gate electrode and the second gate electrode. The dielectric structure is continuous along an entirety of a height of the first gate electrode and the first sub-fin structure.

Integrated circuit structures with backside gate cut or trench contact cut

Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

Integrated circuit structures having cut metal gates with dielectric spacer fill

Integrated circuit structures having backside gate partial cut or backside trench contact partial cut and/or spit epitaxial structure are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first portion of a gate electrode is around the first stack of nanowires, a second portion of the gate electrode is around the second stack of nanowires, and a third portion of the gate electrode bridges the first and second portions of the gate electrode. A dielectric structure is between the first portion of the gate electrode and the second portion of the gate electrode, the dielectric structure over the third portion of the gate electrode. The dielectric structure is continuous along the first and second portions of the gate electrode and the first and second sub-fin structures.

Integrated circuit structures with backside gate partial cut or trench contact partial cut

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Portland, OR, United States of America

Charles Henry Wallace