Lsi Logic Corporation

Verisilicon Holdings Company Ltd.

Verisilicon Microelectronics (shanghai) Co., Ltd.

Charles H Stewart

Keith D Dang

Shannon A Wichman

Asheesh Kashyap

Mark Allen Boike

Alan Phan

Charles R Bezet

The present disclosure is directed to methods to generate a packed result array using parallel vector processing, of an input array and a comparison operation. In one aspect, an additive scan operation can be used to generate memory offsets for each successful comparison operation of the input array and to generate a count of the number of data elements satisfying the comparison operation. In another aspect, the input array can be segmented to allow more efficient processing using the vector registers. In another aspect, a vector processing system is disclosed that is operable to receive a data array, a comparison operation, and threshold criteria, and output a packed array, at a specified memory address, comprising of the data elements satisfying the comparison operation.

Vector compare and store instruction that stores index values to memory

An improved method of operating a digital signal processor instruction pipeline and a memory interface for implementing the method. Memory store requests are separated into an address phase and a data phase. Store addresses are issued to the interface when ready and held in a queue until the corresponding store data is available. The store data is issued to the interface and held in a queue until its corresponding store address is to be coupled to memory. The pipeline operates more efficiently because it does not have to wait for store data before issuing the address and related control signals. Data coherency is maintained because load and store addresses are issued at the same pipeline stage and executed in the order issued.

Increasing DSP efficiency by independent issuance of store address and data

A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.

System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline

The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

Integrated circuit containing multiple digital signal processors

A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The bridge includes a generic slave module which provides direct connections to the on-chip bus in the on-chip bus protocol. It also includes a slave engine connected to the DSP memory interface to control read and write transactions with the memory. The generic slave and the slave engine are coupled by a pulse grower and pulse shaver to allow the engine to operate at DSP clock frequency while the generic slave operates at the usually slower on-chip bus frequency. The bridge allows masters in the ASIC to perform read and write transactions with the DSP internal memory.

Bridge for coupling digital signal processor to on-chip bus as slave

A unique memory access system and method to handle memory access requests to a memory shared by multiple independent data access devices (&ldquo;IDADs&rdquo;). More particularly, the present invention relates to a method and system that allows IDADs to efficiently execute memory access requests without having to wait for the shared memory to be available. In addition, the IDADs do not have to be designed to observe the specific memory protocol. The memory access requests from the IDADs are accepted by access request logic which then queues the requests. Memory access logic then executes the requests from the queue when the shared memory is available. The memory access logic places data obtained from read requests in a read buffer for the IDADs to access when convenient.

Parameterizable queued memory access system

A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol signals. An arbiter is provided to receive the signals from the two DSP interfaces and selectively pass the signals to a generic bus master which couples the signals to the on-chip bus. A synchronization unit is provided to insure alignment of positive clock transitions between the different clock frequencies of the ASIC and the DSP and to buffer signals as needed. The generic bus master couples signals from the arbiter and the synchronization unit to the ASIC bus in full compliance with the bus protocol.

Growing community of inventors

Richardson, TX, United States of America

Charles H Stewart