Patriot Scientific Corporation

Nanotronics Corporation

Harris Corporation

Charles H Moore

Russell H Fish, Iii

Robert W Murphy

A microprocessor integrated circuit including a processing unit disposed upon an integrated circuit substrate is disclosed herein. The processing unit is designed to operate in accordance with a predefined sequence of program instructions stored within an instruction register. A memory, capable of storing information provided by the processing unit and occupying a larger area of the integrated circuit substrate than the processing unit, is also provided within the microprocessor integrated circuit. The memory may be implemented using, for example dynamic or static random-access memory. A variable output frequency system clock, such as generated by a ring oscillator, is also disposed on the integrated circuit substrate.

High performance microprocessor having variable speed system clock

A high performance, low cost microprocessor system having a variable speed system clock is disclosed herein. The microprocessor system includes an integrated circuit having a central processing unit and a ring oscillator variable speed system clock for clocking the microprocessor. The central processing unit and ring oscillator variable speed system clock each include a plurality of electronic devices of like type, which allows the central processing unit to operate at a variable processing frequency dependent upon a variable speed of the ring oscillator variable speed system clock. The microprocessor system may also include an input/output interface connected to exchange coupling control signals, address and data with the central processing unit. The input/output interface is independently clocked by a second clock connected thereto.

A high-performance microprocessor system using instruction that access operands and instructions located relative to the current instruction group rather than located relative to the current instructions, as is the convention, is disclosed herein. The microprocessor system includes a central processing unit, memory, and a bus connecting the central processing unit and memory. An instruction fetching unit, connected to the bus, is provided for fetching instruction groups from the memory for use by the central processing unit and for storage within an instruction register. An instruction supplying unit operates to supply, in succession from the instruction register to the central processing unit, one or more instructions from each of the instruction groups. The system further includes an instruction decoder for configuring the instruction supplying unit to select, from the instruction register, operands associated with instructions from particular instruction groups.

High performance microprocessor using instructions that operate within

A microprocessor including a central processing unit connected to a push-down stack is disclosed herein. The push-down stack includes a first plurality of latches corresponding to a like first plurality of stack elements, and a second plurality of locations of random access memory corresponding to a like second plurality of stack elements. The first and second plurality of stack elements are provided in a single integrated circuit with the microprocessor. The push-down stack further includes a third plurality of memory locations in a system random access memory, with the third plurality of memory locations corresponding to a like third plurality of stack elements. In operation, up to a first plurality of items initially stored in the first plurality of stack elements are transferred therefrom without accessing the second plurality of stack elements. When the first plurality of stack elements are empty, up to a second plurality of items may be transferred thereto from the second plurality of stack elements. Similarly, up to the second plurality of items may be transferred from the second plurality of stack elements without accessing the third plurality of stack elements. In addition, up to a third plurality of items may be transferred from the third plurality of stack elements to the second plurality of stack elements when the second plurality of stack elements become empty.

Microprocessor system with hierarchical stack and method of operation

A data processing system in which timing of data transfer operations are adjusted in response to bus load variation is disclosed herein. The data processing system includes a microprocessor having a sensing circuit, and a driver circuit disposed to impress a signal upon a control line. The control line is also connected to the sensing circuit, as well as to one or more devices external to the microprocessor. The sensing circuit is configured to monitor a response time required for the signal impressed upon the control line to reach a predetermined electrical level, wherein the response time is a function of the number of devices coupled to the control line. The microprocessor is disposed to adjust the timing of data transfer between the microprocessor and the one or more devices external to the microprocessor based upon the monitored response time.

Data processing system having load dependent bus timing

A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down stack (74), which has a top item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register (76) by line (86). The output of the top item register at (82) is also connected by line (88) to an internal data bus (90). A loop counter (92) is connected to a decrementer (94) by lines (96) and (98). The loop counter (92) is bidirectionally connected to the internal data bus (90) by line (100). Stack pointer (102), return stack pointer ( 104), mode register (106) and instruction register (108) are also connected to the internal data bus (90) by lines (110), (112), (114) and (116), respectively. The internal data bus (90) is connected to memory controller (118) and to gate (120). The gate (120) provides inputs on lines (122), (124), and (126) to X register (128), program counter (130) and Y register (132) of return push down stack (134). The X register (128), program counter (130) and Y register (132) provide outputs to internal address bus (136) on lines (138), (140) and (142). The internal address bus provides inputs to the memory controller (118) and to an incrementer (144). The incrementer (144) provides inputs to the X register, program counter and Y register via lines (146), (122), (124) and (126). The DMA CPU (72) provides inputs to the memory controller (118) on line (148). The memory controller (118) is connected to a RAM by address/data bus (150) and control lines (152).

High performance, low cost microprocessor

A microprocessor (50) includes a main central processing unit (CPU) (70) and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making up the microprocessor (50). The main CPU (70) has a first 16 deep push down tack (74), which has a to item register (76) and a next item register (78), respectively connected to provide inputs to an arithmetic logic unit (ALU) (80) by lines (82) and (84). An output of the ALU (80) is connected to the top item register at (82) is also connected by line (88) to an internal data bus (90). CPU (70) is pipeline free. The simplified CPU (70) requires fewer transistors to implement than pipelined architectures, yet produces performance which matches or exceeds existing techniques. The DMA CPU (72) provides inputs to the memory controller (118) on line (148). The memory controller (118) is connected to a RAM by address/data bus (150) and control lines (152). The DMA CPU (72) enables the CPU (70) to execute instructions four times faster than the RAM speed by fetching four instructions in a single memory cycle.

High performance, low cost microprocessor architecture

A microprocessor for facilitating use of FORTH computer language includes a top register for storing a first parameter and an Arithmetic logic unit (ALU) connected to the top register for processing the first parameter with other parameters and for storing the results in the top register. An index register stores a second parameter and addresses main memory and pops and pushes the second parameter with respect to a return Last in/first out (LIFO) stack. A next parameter register stores a third parameter and pops andpushes the third parameter with respect to a next parameter LIFO stack. Anh addressing multiplexer is coupled to the index register and the next parameter register. A first swap connection to the top and index registers enables single cycle exchange of the first and second parameters between these two registers. A second swap connection between these registers permits a single cycle exchange of the first parameter and the third parameter between the top and next parameter registers. The memory, return LIFO, stack and next parameter LIFO stack comprise discrete and separate memory areas not accessible.

FORTH specific language microprocessor

A language specific microprocessor for the computer language known as FORTH is disclosed. The microprocessor includes four main registers each for holding a parameter; a L or instruction latch register for decoding instructions and activating microprocessor operation; an I or return index register for tracking returns; an N or next parameter register for operation with an arithmetic logic unit (ALU); and a T or top of parameter stack register with an appended ALU. A return stack port is connected to the I register and a parameter stack port is connected to the N register circuit, each have last in/first out (LIFO) memory stacks for reads and writes to isolated independent memory islands that are external to the microprocessor. The respective I, T and N registers are connected in respective series by paired bus connections for swapping parameters between adjacent registers. A first split 16 bit multiplexer J/K controls the LIFO stack for the I and N registers on paired 8 bit address stacks; a second 16 bit multiplexer designates the pointer to main memory with 65K addresses and an adjoining 65K for data. This addressing multiplexer receives selective input from a program counter P, the return index register I, the top of the parameter stack T and/or the instruction latch L. Movement to subroutine is handled in a single cycle with returns being handled at the end of any designated cycle. Asynchronous microprocessor operation is provided with the address multiplexer being simultaneously set up with an address to a future machine step, unloading from memory of appropriate data or instruction for the next machine step and asynchronously executing the current machine step. A two-phase clock latches data as valid on a rising edge and moves to a new memory location on a falling edge. This two phase clock is given a pulse width sufficient for all asynchronous cycles of microprocessor operations to settle. The microprocessor's assembler language is FORTH and the stack and main memory port architecture uniquely complements FORTH to produce a small (17,000 gates) fast (40 mips) microprocess or operable on extant FORTH programs. Provision is made for an additional G port which enables the current operating state of the microprocesor to be mapped, addressing of up to 21 bits as well as the ability to operate the microprocessor in tandem with similar microprocessors.

Growing community of inventors

Woodside, CA, United States of America

Charles H Moore