Hrl Laboratories, LLC

Other

Hughes Electronics Corporation

Charles H Fields

Adele E Schmitz

Kursad Kiziloglu

Stephen Thomas, Iii

A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.

HBT with emitter electrode having planar side walls

HBT with configurable emitter

The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pand leaving a pattern according to the mask in the resist; depositing base metal on the entire surface; and removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xfrom 0.05 &#x3bc;m to 0.7 &#x3bc;m. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.

Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing

The present invention improves the yield of integrated circuit manufacture by making the circuit more tolerant of varying thicknesses of the InterLayer Dielectric prior to metallization and interconnection. The sensitivity to the thickness of the ILD is reduced by first coating the devices with an etch stop layer, exposing the areas of the devices where interconnections will be made, selectively etching away the etch stop layer over the interconnection areas, adding the Interlayer Dielectric and then finally etching away the ILD to expose the contacts and continuing the processing through interconnection of the devices.

Bilayer dielectric interconnection process

The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pand leaving a pattern according to the mask in the resist; removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance x. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.

Non-self-aligned heterojunction bipolar transistor and a method for preparing a non-self-aligned heterojunction bipolar transistor

A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.

Thin film devices and method for fabricating thin film devices

High-speed, low capacitance heterojunction bipolar transistors (HBTs) and a method for their fabrication are disclosed. The devices are fabricated by a manufacturable process which moves patterning and deposition of the base post up versus the current manufacturing process, thus permitting fabrication of a smaller base post and base metal contact and reducing the base-collector capacitance.

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Calabasas, CA, United States of America

Charles H Fields