Micron Technology Incorporated

Ovonyx Inc.

Intel Corporation

Micron Semiconductor, Inc.

Round Rock Research, LLC

Stmicroelectronics S.r.l.

Other

Charles H Dennison

Monte Manning

Trung Tri Doan

Pierre C Fazan

Kunal R Parekh

Yauh-Ching Liu

John K Zahurak

Mark Fischer

Richard H Lane

Aftab A Ahmad

Howard E Rhodes

Brent Keeth

Tyler A Lowrey

Mark Alan Helm

Ruojia R Lee

Brian M Shirley

Mark E Jost

John David Hopkins

Gordon A Haller

Michael A Walker

Stephen J Hudgens

Hiang C Chan

David L Dickerson

Hongbin Zhu

Shubneesh Batra

Kevin J Ryan

Chien Chiang

Ken W Marr

Akira Goda

Krishna Kumar Parat

Fatma Arzum Simsek-Ege

Roger R Lee

Todd R Abbott

Jeffrey W Honeycutt

Raymond A Turi

Fawad Ahmed

Troy A Manning

Randhir P Thakur

Stephen L Casper

Chris G Martin

Anish A Khandekar

Jie Sun

Chih-Chen Cho

Brett D Lowe

Brian L Brown

Brian J Cleereman

Merri Lyn Carlson

Brian G Johnson

Ming-Bo Liu

Christopher B Cooper

Jia Hui Ng

Lining He

Fernando N Gonzalez

Guy T Blalock

Michael P Violette

Jigish D Trivedi

Philip J Ireland

Kenneth William Marr

Deepak Thimmegowda

Steven D Cummings

Alice T Wang

Jenn C Chow

Gurtej S Sandhu

H Montgomery Manning

John Heck

D Mark Durcan

Derchang Kau

Guy Charles Wicker

Wolodymyr Czubatyj

Ward D Parkinson

Ilya V Karpov

Bradley J Howard

Haisheng Rong

Viju K Mathews

Randal W Chance

Daniel Xu

Harel Frish

George A Gordon

Jeffrey B Driscoll

Jonathan K Doylend

Akram Ditali

John M Peters

Kanaiyalal Patel

Carl Schell

George A Ghiurcan

Michael E Favaro

Patel Kanaiyalal Chaturbhai

Roy Maddox

A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure

Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a substrate, a waveguide disposed above the substrate, a phase change layer disposed above the waveguide, and a heater disposed above the phase change layer. The waveguide has a modifiable refractive index based at least in part on a state of a phase change material included in the phase change layer. The phase change material of the phase change layer is in a first state of a set of states, and the waveguide has a first refractive index determined based on the first state of the phase change material. The heater is to generate heat to transform the phase change material to a second state of the set of states, and the waveguide has a second refractive index determined based on the second state of the phase change material. Other embodiments may also be described and claimed.

Semiconductor photonic devices using phase change materials

Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

Integrated structures and methods of forming vertically-stacked memory cells

Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Floating gate memory cells in vertical memory

Integrated structures

Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

Apparatuses and methods for die seal crack detection

In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. In one embodiment, a face centered cubic chalcogenide structure may be utilized.

Semiconductor phase change memory using face center cubic crystalline phase change material

In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

Semiconductor phase change memory using multiple phase change layers

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Meridian, ID, United States of America

Charles H Dennison