Texas Instruments Corporation

Charles Gerlach

Rejitha Nair

Kazunobu Shin

Siva Srinivas Kothamasu

Chunhua Hu

Venkateswar Reddy Kowkutla

Venkateswara Reddy Pothireddy

John Chrysostom Apostol

Raghavendra Santhanagopal

Ravi Teja Reddy

Rajagopal Kollengode Ananthanarayanan

A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.

Power-on-reset signal isolation during lower power mode

In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.

Integrated circuit with low power mode management

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DALLAS, TX, United States of America

Charles Gerlach