Massachusetts Institute of Technology

Other

Kabushiki Kaisha Toshiba

Nec Corporation

Analog Devices,inc.

The Chinese University of Hong Kong

Sensata Technologies, Inc.

Smal Camera Technologies, Inc.

Charles G Sodini

Hae-Seung Harry Lee

Hirofumi Yamashita

Grant Seaman Anderson

Jon P Wade

Keith Glen Fife

Tohru Kimura

Michael Henderson Perrott

Anantha P Chandrakasan

Jason Sproul

Ichiro Masaki

Ni Zhao

Jing Liu

Kailiang Chen

David Da He

Edward T Chang

Tom O'Dwyer

Frederick P Herrmann

John K Fiorenza

Todd Sepke

Eric Steven Winokur

Pablo M Acosta-Serafini

Devices and methods for non-invasive capillary blood pressure measurement are provided. An device can comprise a front end in contact with the body to compress and decompress the capillaries in the tissue, a pressure control module for regulating the contact pressure between the front end and the tissue, a pressure transducer coupled to the front end for measuring the contact pressure, a capillary sensing module for detecting the capillaries pulsations under the contact pressure modulation, and an algorithm for determining the capillaries pressures from the traces of capillary pulsation signals and the contact pressure signal. The methods include an oscillometric method for intermittent arterial and capillary blood pressure measurement and a volume-clamp method for continuous capillary blood pressure measurement.

Devices and methods for non-invasive capillary blood pressure measurement

An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a N&#xd7;M array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the N&#xd7;M array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.

Application specific integrated circuit with column-row-parallel architecture for ultrasonic imaging

Buffered body return receiver configurations are described. An amplifier for a receiver can be connected to two electrodes such that one of the two electrodes is connected to a non-inverting input of the amplifier and a second of the two electrodes is a driven node by being connected to both the inverting input of the amplifier and the output of the amplifier. The amplifier may be connected as a fully differential amplifier, a single-ended differential amplifier, a buffer, or an amplifier with a gain greater than 1, while still enabling improved channel gains with reduced power consumption at the transmitter from the signal source. The buffered body return receiver is suitable for scenarios in which a signal source is electrically independent of the power supply of the receiver's amplifier.

Buffered body return receiver

Systems, apparatus, and methods of asynchronous digital communication include at least one transmitter and/or at least one receiver communicatively coupleable to at least one communication interface for encoding and transmitting digital information as and/or receiving and decoding digital information from a transition between a first symbol and a second symbol, based on a predetermined relationship between the first symbol and the second symbol in such a way that the timing of the symbols is no longer relevant.

Asynchronous digital communication

A circuit for expanding a dynamic range. In one embodiment, the circuit includes: a transducer generating a signal current on an output terminal in response to a physical quantity, the signal current comprising an AC current and a DC current; a dynamic range enhancement circuit having a digital control signal input terminal and producing a variable opposition current in response to a digital signal applied to the digital control signal input terminal; an amplifier; an analog to digital converter in electrical communication with the amplifier; and a digital feedback circuit in communication with the output terminal of the analog to digital converter and in electrical communication with the digital control signal input terminal of the dynamic range enhancement circuit, wherein the opposition current from the dynamic range enhancement circuit is set substantially equal to the DC current portion of the signal current from the transducer.

Digitally assisted analog dynamic range enhancer

A circuit and method for long term electrocardiogram (ECG) monitoring is implemented with the goal of reducing power consumption, battery size, and consequently device size. In one embodiment, the integrated circuit includes an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell in communication with the output of the amplifier cell; a baseline amplifier cell in communication with the output of the amplifier cell; a comparator cell having a first input terminal in communication with the output terminal of the QRS amplifier cell; and a Vcell having an input in communication with the output of the baseline amplifier cell and an output in communication with the second input terminal of the comparator cell, wherein the comparator cell generates an output pulse in response to the output signal from the amplifier cell and the output signal from the baseline amplifier cell.

Circuit for heartbeat detection and beat timing extraction

A system and method process non-linear image data, still or video, from a digital imager. Noise generated by analog-to-digital converters is filtered from a pixel of digital image data. Moreover, the effects of single pixel defects in the imager are eliminated by clamping a predetermined pixel of image data within the window when the value of the predetermined pixel is greater than a maximum value of the image data of neighboring pixels or less than a minimum value of the image data of neighboring pixels. Ripples in image data are reduced by eliminating the effects of single pixel defects before filtering for crosstalk caused by electrical crosstalk between sensor elements in an imager. Dark current is removed from image data generated by an imager by subtracting a fraction of a determined dark current value from all image data generated by the imager to compensate for nonlinearities in dark current across the imager. The image data is white balanced by creating a set of scalar color adjustments from determined average color values and constraining the set of scalar adjustments to plausible lighting conditions to prevent overcompensation on images having large regions of similar hue. Lastly, utilization of a fixed set of intensity levels is optimized by remapping and restreching the image data to create new luma values for each pixel.

System and method for processing non-linear image data from a digital imager

Described is a switched capacitor circuit for performing an analog circuit function. Unlike conventional switched capacitor circuits employing operational amplifiers, the switched capacitor circuit uses a comparator and does not require direct feedback between the input and output of the comparator. The switched capacitor circuit includes a first and a second switched capacitance network, a comparator and a current source. The first switched capacitance network has an input terminal to receive a circuit input voltage during a first phase. The comparator has an input terminal in communication with the first switched capacitance network and an output terminal in communication with the second switched capacitance network through a switched terminal. The current source communicates with the switched capacitance networks and supplies a current to charge the networks during a second phase. The circuit can be used, for example, to provide high gain amplification in integrated circuits.

Comparator-based switched capacitor circuit for scaled semiconductor fabrication processes

The imager system of the invention, provided in a semiconductor substrate, includes a plurality of photosensitive, charge integrating pixels that are arranged in rows and columns of a pixel array for capturing illumination of a scene to be imaged. Each pixel includes a photogenerated charge accumulation region of the semiconductor substrate and a sense node at which an electrical signal, indicative of pixel charge accumulation, can be measured without discharging the accumulation region. Pixel access control circuitry is connected to pixel array rows and columns to deliver pixel access signals generated by the access control circuitry for independently accessing a selected pixel in the array. An input interface circuit is connected to accept a dynamic range specification input for the array pixels. Integration control circuitry is connected to access a selected pixel of the array to read the sense node electrical signal of the selected pixel, and configured to generate pixel-specific integration control signals delivered to the selected pixel, independent of other pixels, based on dynamic range specification input provided by the input interface circuit. An output interface circuit is connected to the pixel array to produce output image data based on sense node electrical signals from the pixel array.

Single-chip imager system with programmable dynamic range

An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.

Data input/output configuration for transfer among processing elements of different processors

There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels. The application by the switch circuit of each of the charge control voltages to a row of pixel reset nodes is characterized by a voltage application settling time, t , that is less than about 1/Nrf, where N is an integer and f is imager frame rate. This provides the ability to implement a desired transfer function, to expand imager dynamic range, in a manner that is immune to capacitances of the imager, by causing the voltage spikes, or glitches, associated with imager row capacitance, to decay substantially completely during the time over which an imager pixel row is accessed to apply a control voltage.

Precise MOS imager transfer function control for expanded dynamic range imaging

Image input system including solid image sensing section and signal processing section

A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency. This digital processor is connected to the phase locked loop frequency divider to modulate the divider based on the digitally-processed input modulation data, whereby a voltage controlled oscillator of the phase locked loop is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency. The digital processing of the modulation data can be implemented by adapting a digital FIR Gaussian transmit filter such that its filter characteristic reflects the intended modulation data amplification as well as enables Gaussian Frequency Shift Keyed modulation. With this implementation, no additional componentry beyond the PLL system is needed to implement the digital modulation data processing provided by the invention.

Digital compensation for wideband modulation of a phase locked loop

In a logic integrated DRAM LSI with SIMD architecture, a intentional clock skew is introduced for both between DRAM blocks and between logic blocks due to reduce the magnitude of peak current, operation frequency and number of I/O are defined for both DRAM blocks (frequency f.sub.M, I/O number m) and logic blocks (frequency f.sub.N, I/O number n) to keep the relation of

Circuit technique for logic integrated DRAM with SIMD architecture and a

A logic circuit for a content-addressable-memory or parallel-processor array cell implements both prioritizing and counting functions for response resolution. It includes a means for receiving from a prior cell a response-resolution token and a means for receiving the positive or negative response of the current cell to a pattern to be matched. It also includes a means for deriving as a function of the prior cell's response-resolution token a response-resolution token for the current cell that implements prioritization and counting response-resolution functions for positive or negative pattern-matching responses of the current cell. Finally, it includes a means for selecting for the current cell the appropriate response-resolution token based on the cell's positive or negative pattern-matching response and a means for sending that response-resolution token to a subsequent cell. In a preferred embodiment of the invention, the means for selecting the current cell's response-resolution token for a positive or negative pattern-matching response uses a simple pass-transistor switching circuit.

Growing community of inventors

Belmont, MA, United States of America

Charles G Sodini