Texas Instruments Corporation

Zyvex Corporation

Charles G Roberts

Sebastian R Borrello

Shawn T Walsh

Arturo Simmons

Jaroslav Hynecek

Gregory A Magel

George Dee Skidmore

Dean Robert Collins

Joseph E Hall

Wayne W Chan

Fabricating electrical isolation properties into a MEMS device is described. One embodiment comprises a main substrate layer of a high-resistivity semiconductor material, such as high-resistivity silicon. The high-resistivity substrate is then controllably doped to provide a region of high-conductivity in the main substrate. Electrical isolation is achieved in such an embodiment by patterning the high-conductivity region either by masking the main substrate during the doping or etching through the doped, high-conductivity region in order to form regions of high conductivity. Effective isolation results from confinement of electrical currents to the lowest-resistance path. An alternative embodiment employs the fabrication of pn junctions and the use of reverse biasing to enhance the electrical isolation. A further embodiment comprises a main substrate layer of low-resistivity semiconductor material with a layer of insulator deposited thereon. High-conductivity or low-resistivity material is then grown on top of the insulator to create electrically isolated conductors.

Apparatus and fabrication methods for incorporating sub-millimeter, high-resistivity mechanical components with low-resistivity conductors while maintaining electrical isolation therebetween

An infrared detector in the form of a focal plane array containing infrared detectors of two sensitivity types is disclosed. The detectors may be based on alloys of HgCdTe with cutoff wavelengths of 5 microns and 10 microns. The two types of detectors are in close proximity and thereby avoid the time delay problem. The two spectral sensitivities make possible the determinaton of spectral signatures and target identification. Further, the two types of detectors are arrayed to permit use of a single set of read lines together with electronic addressing for selecting the detector type, thereby simplifying the output structure and processor design.

Two color infrared focal plane array

A method and an apparatus which permits use of a metal-insulator-semiconductor device as an infrared detector. A single layer of metal is provided having an extremely thin portion through which infrared radiation can pass and a thick portion through which infrared radiation cannot pass. Both of these portions together form the MIS (metal-insulator-semiconductor) gate. A voltage is applied to the metal which creates a potential well within the semiconductor substrate below. When the device is exposed to infrared radiation the radiation, causes photons to pass through the thin portion of the MIS gate and generates a charge within the potential well. The thick portion of the MIS gate shields the semiconductor substrate from photons so that no charges are generated in the potential well which is located below this portion of the metal layer. This provides a charge storage region so that the charge which is generated under the thin gate can be stored in the entire potential well created by the gate as a whole. This results in an MIS device having a detector cell which can be several times larger than photon sensitive dimensions. In effect, each detector element can have a storage capacity of a gate biased to ten volts or more. A three design is also disclosed which has the detection region separated from the storage region.

Mis infrared detector having a storage area

The disclosure relates to a system for protecting HgCdTe and the like MIS arrays from breakdown during fabrication due to electrostatic charge buildup on the array capacitors. This is accomplished by building into the structure a short circuit across the capacitor plates with a fuse region therein that will evaporate when a voltage is placed thereacross which is sufficient to cause evaporation and low enough not to damage the capacitors.

Electrostatic discharge protection using thin nickel fuse

A floating gate amplifier in a charge-coupled device (CCD) permitting non-destructive readout, where the floating gate is conductively coupled through a high resistance element to a bias voltage. The floating gate is defined by a lower level of metallization which is embedded in an insulating layer and crosses the charge transfer channel. In one embodiment the floating gate is connected to the source of a metal-oxide-semiconductor transistor and the drain of the transistor is connected to an upper level conductor which is a bias line. In another embodiment, the anode of a diode is connected to the floating gate and the diode cathode is connected to the bias line. A pair of control gates adjacent to and partially overlapping the floating gate transfer charge packets and improve sensitivity. Reading is accomplished by detecting voltages induced on the floating gate by the charge packets.

Floating gate amplifier using conductive coupling for charge coupled

The present invention is embodied in a method of operating a charge-coupled device (CCD) having a non-destructive readout floating gate amplifier to minimize noise on the floating gate. A pair of control gates are adjacent to and partially overlap the floating gate and are electrically insulated therefrom. Noise caused by presetting the floating gate voltage is minimized by presetting after a series of 'reads' instead of after each 'read'. Coherent clock noise induced by capacitive coupling of the control gates to the floating gate is eliminated by applying appropriate simultaneous signals to the control gates. Device sensitivity is improved.

Floating gate amplifier method of operation for noise minimization in

A disk shaped ceramic support has a mounting surface provided as a unitary part of the support with conductors extending generally outward from the mounting surface through the thickness dimension of the support, the outer ends of the conductive leads being connected to a ring of terminal leads. A charge coupled device (CCD) imager chip is secured to the mounting surface to leave a backside illumination surface of the chip unobstructed and electrical interconnections are made from terminal pads on the front surface of the chip to the ends of the conductive leads adjacent the mounting surface. A cover plate attached to the insulating support outwardly of the interconnections encloses the front surface of the chip. In a preferred structure the chip is mounted on an apertured molybdenum disk unitarily attached to the support with the illumination surface of the CCD chip facing the aperture. A peripheral tube flange can be brazed to the periphery of the insulating support and a tubular enclosure vacuum sealed to the tube flange for accommodating a photo-cathode source which faces the illumination surface of the imager chip. In a further embodiment, the front side of the chip is attached directly to a mounting surface provided by the insulating support itself, connections between the terminal pads on the chips and the conductive leads of the support being effected therough apertures in the support located adjacent corners of the chip.

Growing community of inventors

McKinney, TX, United States of America

Charles G Roberts