Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Nxp B.v.

Sigmatel, Inc.

Charles Eric Seaberg

Ravindraraj Ramaraju

Kenneth R Burch

Octavio A Gonzalez

Chang Joon Park

Jon David Hendrix

David R Bearden

Junsong Li

Hector Adrian Sanchez

Stefano Pietri

Shayan Zhang

Mohit Arora

Sanjay Kumar Wadhwa

Andrew Christopher Russell

Matthew Derrell Felder

Jie Su

Gregory J Buchwald

Ricardo Pureza Coimbra

Dale John McQuirk

Bradley J Garni

Khoi Mai

Ivan Carlos Ribeiro Do Nascimento

Prashant Bhargava

Robert Matthew Mertens

Felipe Ricardo Clayton

Simon Gallimore

Ateet Omer

Javier Mauricio Olarte Gonzalez

Ravichandar Reddy Geetla

Azfar Inayatullah

Bradley A Banks

A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

Clock generator with noise rejection circuit

An integrated circuit that can include a driver having a first driver output, and a first resistance coupled between a first node coupled to the first driver output and a second node. The first resistance can include a process resistor including a first material having a first temperature coefficient, and an interconnect resistor configured to provide at least 20% of the first resistance and including a second material having a second temperature coefficient which changes resistance in an opposite direction with temperature as compared to the first temperature coefficient. A first terminal of the interconnect resistor is directly connected to a first terminal of the process resistor.

Temperature compensation for silicon resistor using interconnect metal

A receiver includes an input node coupled to receive an analog signal, a first switch coupled between the input node and a first node, a second switch coupled between the input node and a second node, a first resistive element coupled between the first node and a reference node, a second resistive element coupled between the second node and the reference node, a first capacitive element coupled to the first node, and a second capacitive element coupled to the second node. The receiver also includes a comparator having a first input coupled to the input node to receive the analog signal, and a second input coupled to the reference node to receive a reference voltage, wherein an output of the comparator controls the first and second switches.

Tracking voltage reference for single ended receiver

A temperature sensor configured to, after a predetermined number of stop counting assertions, determine the temperature dependent voltage and thus the temperature at the output of a counter. During a calibration phase, when a counter value is not equal to a test counter value in a pulse generator circuit, capacitance of the temperature sensor is adjusted until the counter value is equal to the test counter value.

Temperature sensor in an integrated circuit and method of calibrating the temperature sensor

A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Back bias regulator circuit and method therefor

A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.

Data processing system with temperature monitoring for security

A circuit includes a first transistor having a first current electrode coupled to a first power supply node, a second current electrode coupled to a switching node; a second transistor having a first current electrode coupled to the switching node, a second current electrode coupled to a second power supply node; an inductor having a first terminal coupled to the switching node, a second terminal coupled to an output node; a third transistor having a first current electrode coupled to the output node, a second current electrode coupled to the switching node; a driver circuit configured to transition the switching node from a first voltage to a second voltage by turning on the third transistor to couple the output node to the switching node during a first time period, turning on the first transistor to couple the first power supply node to the switching node during a second time period.

Switching scheme to extend maximum input voltage range of a DC-to-DC voltage converter

An integrated circuit device includes a driver circuit () having a pull-up network with a first pull-up transistor () coupled to a second pull-up transistor () at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor () coupled to a second pull-down transistor () at a second node (VN). A first bias switch () is coupled to the first node. A second bias switch () is coupled to the second node. A control circuit () is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.

System and method for breakdown protection for switching output driver

Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.

Multistage voltage regulator circuit

A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.

Memory voltage regulator with leakage current voltage control

A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Integrated circuit having low power mode voltage regulator

An audio amplifier includes an output stage for generating an output stage voltage in response to an input signal and an output stage quiescent current. A controlled current source controls the output stage quiescent current in response to a quiescent current signal during a start-up cycle.

Audio amplifier and methods for use therewith

A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.

Circuit for a low power mode

An audio output circuit includes a DAC module, a line out circuit, and a headphone amplifier circuit. The digital to analog conversion (DAC) module is coupled to convert an audio component of digitized multimedia data into an analog audio signal. The line out circuit is coupled to amplify the analog audio signal based on a line out volume setting. The headphone amplifier is coupled to amplify the analog audio signal based on a volume setting to produce an amplified analog audio signal.

System on a chip with multiple independent outputs

Embodiments of the present invention relate generally to digital volume control in digital audio systems. One embodiment relates to a digital audio system having a digital audio processor and a digital volume control coupled to the digital audio processor. The digital volume control includes a feedback loop having an attenuator, and error determination unit, and a filter. The feedback loop determines the attenuation error and shifts the attenuation error beyond a predetermined digital audio range. The output of the digital volume control maintains a substantially constant SNR and THD with respect to the level attenuation over the predetermined digital audio range.

Growing community of inventors

Austin, TX, United States of America

Charles Eric Seaberg