International Business Machines Corporation

Other

Charles Edwin Cox

Martin Aureliano Hassner

Barry Marshall Trager

Ahmet Serkan Ozcan

Shmuel Winograd

James Lee Hafner

Arvind M Patel

Arvind Kumar

Myron Dale Flickner

Pritish Narayanan

Harald Huels

Winfried W Wilcke

Xiao Hu Liu

Nicolas Antoine

Alexis Asseman

Ralph Koetter

Nimrod Megiddo

Jeffrey Owen Kephart

Jehoshua Bruck

David Michael Chess

Steve Richard White

William Carlisle Arnold

J Campbell Scott

Gregory Bret Sorkin

Jimmy Lee Reaves

Gerhard P Fettweis

Uwe Schwiegelshohn

Ralf Kotter

E George Wolf, Jr

Wolf-Ekkehard Blanz

A system according to one embodiment includes a collection of computing nodes arranged in a mesh of N&#xd7;M&#xd7;Z topology, the nodes including computational hardware, wherein Z&#x3c;N and Z&#x3c;M, and wherein N and M are at least equal to 4; a collection of I/O connections interfaced with one of the sides of the mesh, said side having N&#xd7;M nodes, each of the I/O connections being tied to a unique one of the nodes in said side; and I/O cards that are tied to the I/O connections.

Configuring computing nodes in a three-dimensional mesh topology

A method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (p) from p using the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein a notation jrepresents the xbit of j from the right, with bit jbeing the rightmost bit of j.

Fixed value multiplication using field-programmable gate array

A computer-implemented method is provided for use with a reconfigurable computational device having a collection of computing nodes arranged in a mesh of N&#xd7;M&#xd7;Z topology, the computing nodes including computational hardware, wherein Z&#x3c;N and Z&#x3c;M, and wherein N and M are at least equal to 4. The method includes using the computational device to perform computations characterized by (i) an initial system I/O bandwidth and (ii) an initial system node-to-node latency; reconfiguring the device into a mesh of N'&#xd7;M&#x2032;&#xd7;Z&#x2032; topology, wherein at least two of N, M, and Z values are different from their corresponding N&#x2032;, M&#x2032;, and Z&#x2032; values, and wherein N&#xd7;M&#xd7;Z is equal to N&#x2032;&#xd7;M&#x2032;&#xd7;Z&#x2032;; and using the device to perform computations characterized by (i) a modified system I/O bandwidth and (ii) a modified system node-to-node latency.

A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Wafer-scale power delivery

Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.

High memory bandwidth neuromorphic computing system

A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record.

Method and system for emulating content-addressable memory primitives

An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.

Root solver and associated method for solving finite field polynomial equations

An on-the-fly algebraic error correction system and corresponding method for reducing error location search are presented. The method transforms an error locator polynomial into two transformed polynomials whose roots are elements in a smaller subfield, in order to significantly simplify the complexity, and to reduce the latency of the error correcting system hardware implementation. More specifically, if the error locator polynomial is over a finite field of (2 ) elements, the transformed polynomial is over a finite subfield of (2 ) elements. Thus, the problem of locating the roots of the error locator polynomial is reduced to locating the roots of the transformed polynomials. Assuming the error locator polynomial is of degree m, the present method requires at most (m /2) evaluations of polynomials over the Galois field GF(2 ) and (2 ) evaluations over the subfield GF(2 ) or root finding of two polynomials of at most a degree m over the subfield GF(2 ).

On-the-fly algebraic error correction system and method for reducing error location search

A method and apparatus for ensuring the integrity of data that can detect errors that remain when the data correction scheme fails to correct at least some of the errors, or has added additional errors. Reed-Solomon check symbols are used for error correction and cyclic redundancy check symbols are used to detect the remaining errors. The roots of the generator polynomials used to generate the Reed-Solomon check symbols and the cyclic redundancy check symbols meet a selected subset of a plurality of conditions. The roots are further selected so that the necessary exponentiation may be performed by a combination of exponentiations by powers of two and multiplications. The Reed-Solomon check symbols are generated based on the data portion of the data block. A deterministically altered data stream is generated based on the data portion of the data block and the cyclic redundancy check symbols are generated based on the deterministically altered data stream. The deterministically altered data stream is generated by performing an operation on a symbol of the data portion based on a position of the symbol within a Reed-Solomon codeword.

Method and apparatus for updating cyclic redundancy check information for data storage

Method and apparatus for deterministically altering cyclic redundancy check information for data storage

A composite encoder/syndrome generating device that both computes check symbols over counterpart data symbol strings to form codewords, and derives syndromes from codewords indicative of their error state. The multistage device provides recursive processing paths at each stage of depth corresponding to the number of symbols concurrently applied to the device. The device is adapted as an encoder when the feed-forward paths between stages are enabled; it is adapted as a syndrome generator upon their disablement. The number of symbols concurrently processed may be varied from clock cycle to clock cycle by conforming the recursion paths per stage to the number of symbols applied as input to the device.

Parallelized programmable encoder/syndrome generator

A method of decreasing the permeabilty of dentin by the application of an effective amount of oxalic acid potassium salt, dihydrate in an aqueous solution at a pH of about 2.0 to 4.0 to the dentin.

Acid resistant film forming dental composition and method of use

A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t&lE;5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Method and means for computationally efficient on-the-fly error correction in linear cyclic codes using ultra-fast error location

A system for continuous monitoring and autonomous detection of patterns in the main memory subsystem of a computer system. The invention can be embodied as an extension to existing memory scrubbing hardware to permit stored code pattern analysis and identification during the autonomous transparent memory scrubbing process. A library of stored target signatures is provided to which code signatures are compared during analysis. Code signatures may be derived directly from the memory subsystem data pattern or may be indirectly and more efficiently derived from the error correction code (ECC) string associated with the stored data pattern. This invention is directly applicable to computer virus detection and neutralization systems.

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San Jose, CA, United States of America

Charles Edwin Cox