Intel Corporation

Seagate Technology Incorporated

Hewlett-Packard Development Company, L.p.

Lsi Corporation

Compaq Computer Corporation, Inc.

Charles Edward Peet

David Allen Brown

Chris Randall Stone

David Sonnier

Shashank Nemawarkar

Balakrishnan Sundararaman

William P Bunton

John C Krause

Allen Vestal

Siddharth Krishna Kumar

William J Watson

Michael R Betker

David T Heron

Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Method and apparatus to perform a function level reset in a memory controller

Systems and methods are disclosed to delete a command queue, in accordance with certain embodiments of the present disclosure. An apparatus may comprise a circuit configured to receive a queue deletion indicator from a host device, including a queue identifier for a selected command queue to be deleted. The circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier. Commands associated with the selected queue may be identified in a command table and flagged with an abort bit, which may signal an I/O processing pipeline to abort the command when encountered. The circuit may verify that no commands associated with the selected command queue remain pending at the apparatus, and send a completion indicator to notify the host device that the selected command queue is deleted.

Method and apparatus to delete a command queue

Described embodiments provide for storing data in a local cache of one of a plurality of processing modules of a network processor. A control processing module determines presence of data stored in its local cache while concurrently sending a request to read the data from a shared memory and from one or more local caches corresponding to other of the plurality of processing modules. Each of the plurality of processing modules responds whether the data is located in one or more corresponding local caches. The control processing module determines, based on the responses, presence of the data in the local caches corresponding to the other processing modules. If the data is present in one of the local caches corresponding to one of the other processing modules, the control processing module reads the data from the local cache containing the data and cancels the read request to the shared memory.

Data caching in a network communications processor architecture

Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.

Tracking written addresses of a shared memory of a multi-core processor

Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request.

Described embodiments provide a method of coordinating debugging operations in a network processor. The network processor has one or more processing modules. A system cache of the network processor requests a data transfer between the system cache and at least one external memory. A memory interface of the network processor selects an encrypted data pipeline or a non-encrypted data pipeline based on whether the processed data transfer request includes an encrypted operation. If the data transfer request includes an encrypted operation, the memory interface provides the data transfer to the encrypted data pipeline and checks whether a debug indicator is set for the data transfer request. If the debug indicator is set, the memory interface disables encryption/decryption of the encrypted data pipeline. The data transfer request is performed by the encrypted data pipeline to the at least one external memory.

Configurable memory encryption with constant pipeline delay in a multi-core processor

A multiprocessor or clustered system with processing elements communicatively interconnected transmits and receives data in the form of message packets. Certain of the message packets are either responding to earlier requests with the data, or are requests that the data of the packet be written at the destination. Each message packet has an initial portion that includes information about the packet, including what the data is carrying (i.e., data in response to an earlier request, or data to be written), the source and ultimate destination of the message packet. This information prevents errant data being written at the destination by determining if the source has &ldquo;permission&rdquo; to send such data to the destination. When a message packet carrying data is received, processing of the packet is started in parallel with continued reception of the data it carries by using the information contained in the initial portion to check the permissions.

Data communication with speculative reception of data in a data processing system

An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.

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Austin, TX, United States of America

Charles Edward Peet