International Business Machines Corporation

Charles Edward Kuhlmann

Ann Marie Rincon

Charles Steven Lingafelt

Norman Clark Strole

Robert Thomas Bailis

Francis Edward Noel, Jr

Richard Gerard Hofmann

Silvio Dragone

Andreas Christian Doering

Andreas Guenther Herkersdorf

Thomas Alan Millard

David Carroll Challener

John Peter Karidis

Bechara F Boury

Terence J Lohman

Charles Joseph Sannipoli

Shahram Salamian

James T Tsevdos

Rosemary Venema Slager

Ronald E Valli

Carl Henry Grant

Eugene M Thomas

Jace W Krull

Neil W Songer

Provision to a customer of equipment already installed into a specified enclosure to create an assembly is accomplished in an advantageous manner by the disclosed process. A manufacturer obtains the enclosure and the components of the specified equipment, installs the equipment in the enclosure and performs appropriate tests on the completed assembly before sending the assembly to the customer.

Provision of custom configured assemblies

A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable 'on the fly', i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration

A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable 'on the fly', i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.

System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration

A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state machine can be used to control a centralized power management control unit or to control a distributed power management unit where each processing element includes its own state machine. The function of the power management state machine can be implemented in any combination of software and/or hardwired logic, depending on the system design requirements. The monitoring and control are implemented through the use of a power management state change algorithm. The determination of the power state of a processing element accommodates interdependencies between the elements. It also makes adjustments in gain factors in response to actual performance and utilization of the network processor.

Network processor power management

A multimedia presentation apparatus and method by which a presenter is freed from the requirement of having or providing or transporting a supporting computer system such as the notebook or laptop system by the incorporation of computing capability and an accessible data port into the housing of the apparatus through which an executable data file may be delivered to cause generation of the desired presentation.

Multimedia presentation apparatus and method

An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such as laptops, to these peripherals. The connector utilizes a programmable Network Processor (NP) either in the host device or in an external fan-out box. This programmable Network Processor adapts the host device to a variety of peripheral devices utilizing different protocols and I/O speeds. The NP can use a Digital Signal Processor to provide programmable services to the physical layers. The host device may contain a high-speed communication interface with the NP contained in the external connection box.

Universal network interface connection

An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality of internal signals from the plurality of logic functions. Finally, the ASIC includes a field programmable (FP) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FP function provides access to internal signals for observation and control. An ASIC using a field programmable gate array (FPGA) function within a standard cell design is utilized to create an internal-to-the-ASIC bridging of internal signals to observe and control of the internal signals of the ASIC. By the placement of logic, which expresses a test program, into the FPGA function that manipulates the I/O pins and/or other functional entities of interest, the ASIC function and/or surrounding logic can be easily verified. In addition, through this system, internal and/or system (external-to-the-ASIC) conditions can be observed. Furthermore, a sequence of resets to different functional blocks can be executed utilizing a system and method in accordance with the present invention. Finally, through this system the end user of the ASIC could write their own error condition correction FPGA code which would communicate using protocols of the existing system error condition architecture.

Method and system for use of a field programmable function within an application specific integrated circuit (ASIC) to access internal signals for external observation and control

An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows &ldquo;field selection&rdquo; of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.

Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity

A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor. Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic. Through a system and method in accordance with the present invention a business process is also provided whereby an ASIC customer can either submit a custom logic file to a vendor or choose from a library of functions to program into the FPGA portion of the chip.

Field programmable network processor and method for customizing a network processor

An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell, the standard cell including a plurality of logic functions. The ASIC also includes an input/output (I/O) configuration function coupled to at least a portion of the logic functions. The ASIC further includes a field programmable gate array (FPGA) function coupled to the I/O configuration function. The FPGA function controls the I/O configuration function based upon a configuration file. A system in accordance with the present invention reduces the cost and time associated with the timing analysis activities during development. An FPGA function within the ASIC is utilized to control the I/O characteristics such as delay, termination and/or slew rate for the I/O pin mapping. Different I/O configurations will be provided by the FPGA function depending on the environment the ASIC is used in. By providing an ASIC that is adaptable to different timing criteria through FPGA programming, the timing analysis performed by the user of the ASIC will be substantially reduced, resulting in a reduction of the development cycle.

Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics

An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization. Access to these registers can be controlled by a simple muxing structure that allows the FPGA to have direct access to the registers when the chip initialization sequence takes place (Chip_Init signal is asserted) and allows the processor bus to have access after initialization is complete (Chip_Init signal is de-asserted).

Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC

An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell. The standard cell includes a plurality of logic functions. The ASIC further includes a field programmable (FP) logic function for coupling the plurality of logic functions together via a plurality of input and output stages. The FP logic function can be programmed for field repair of at least one of the plurality of the logic functions. A method and system in accordance with the present invention utilizes a distributed field programmable logic block in conjunction with standard cells to provide for field repair and improved redundancy. To describe the features of the present invention in more detail, refer now to the following description in conjunction with the accompanying drawings.

Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits

A compact media drive for use in personal computers has a media support and detector arm structure that ejects to extend external of the drive case at the insertion slot to receive corners of a unit of media during data operations. The arm(s) retract within the drive case or system case when no media is received. This allows a drive case to be proportioned with a drive hub for the media adjacent to the insertion slot to reduce the dimension there between from that for normal full disk insertion. The arm structure permits the drive to collect state information at the rear disk corners necessary to avoid incorrect data operations while a significant portion of the disk remains outside the insertion slot.

Compact media drive having retractable media support

An arrangement and method for arbitration to enable split transaction bus protocols provides for a slave to assert a mask signal that sets a mask bit in a mask register when the slave is not ready to complete a requested transaction. A requesting master is forced off the bus and prevented from re-arbitrating while the mask bit is set in the register. When the slave is ready to complete the transaction, a release master signal is asserted which causes the bit in the shift register to be reset. The requesting master is then able to re-arbitrate for use of the bus to complete the transaction. The usable bandwidth of the bus is increased since other masters are able to arbitrate and use the bus until the slave is ready to complete the transaction with the first requesting master.

Growing community of inventors

Raleigh, NC, United States of America

Charles Edward Kuhlmann