Texas Instruments Corporation

Charles E Williams

Taylor R Efland

Quang X Mai

Marco Corsi

Donald Charles Abbott

Louis N Hutter

Chi-Cheong Shen

John P Erdeljac

Dale J Skelton

Stephen A Keller

Konrad Wagensohner

Walter Bucksch

Lesli A Derryberry

Gary L Beene

William R McKee

Joseph D Luttmer

Dennis D Davis

Buford H Carter, Jr

Milton Lee Buschbom

David R Kee

Kent R Carson

Elwin L Johnson

Stephen T Tso

Alex A Oscilowski

Peter Zogas

Thomas D Petrovich

An integrated circuit device ( ) with a bonding surface ( ) directly over its active circuitry, and a method of making such integrated circuits (FIGS. A- E). To make the bonding surface ( ), a wafer ( ) is provided with vias ( ) to its metallization layer ( ) and then coated with a seed metal layer ( ). A plating pattern ( ) is formed on the wafer ( ), exposing portions of the seed metal layer ( ) and blocking the rest of the seed metal layer ( ). These exposed portions are plated with successive metal layers ( ), thereby forming a bonding surface ( ) having a number of layered stacks ( ) that fill the vias ( ). The plating pattern and the nonplated portions of the seed metal layer ( ) are then removed.

Integrated circuit with bonding layer over active circuitry

A method and apparatus for uniformly solder plating leads on semiconductor packages wherein the leads are rotated during the solder plating process and the solder on the leads in planarized and solder between and bridging the leads is removed by the application of a hot gas to the device having the leads. The hot gas is preferably N,which is inert to the process flow at the point in the process when it is utilized.

Semiconductor package lead plating method and apparatus

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art. In one embodiment, the copper surface level interconnect layer (35) is coated with a thin barrier layer of material (37) which may receive a bond wire. The entire structure is then encapsulated in a plastic package (22) such that the plastic is in physical contact with the copper interconnect metal (35). The use of the plastic packaging (22) in physical contact with the copper interconnect metal (35) eliminates the need for the passivation layers of the prior art. Other devices and methods are described.

Plastic encapsulation for integrated circuits having plated copper top

A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).

Method of forming improved thick plated copper interconnect and

A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The barrier member (88) may be disposed between the bondable member (86) and the copper lead (50).

Thick plated interconnect and associated auxillary interconnect

A bond pad (18, 58) may comprise a base (20, 60) of bondable material. The base (20, 60) may have a periphery (26, 66). A segment of an interconnect (24, 64) may contact an extended section (28, 68) of the periphery (26, 66) to electrically couple the interconnect (24, 64) to the bond pad (18,58). The interconnect (24, 64) may comprise a material less resistive than the bondable material.

Bond pad for integrated circuit

The invention is to a header for a power semiconductor device and a method for making the header. A ground pin is mounted or formed on the header mounting base and a header ground lead is placed over the ground pin and fused to the pin by a laser beam.

Laser bond header

A chip carrier with improved packing density, wherein at least one layer of chips is bonded not directly to the substrate, but rather to a heat plate which attaches over the chip cavity and inside the hermetic sealing lid. The heat plate has openings in it to permit attachment of the leads from the chips in the upper layer to bond pads on a bonding ledge inside the cavity of the chip carrier, after the heat plate is emplaced. Each bonding ledge is preferably made somwhat wider than it would otherwise be, and the leads from multiple layers of chips are preferably bonded onto the same bonding ledge.

High-density package

A chip carrier with multiple through hole vias in its hermetic sealing lid. One or more chips is mounted on the inner surface of that lid. The lid contains multiple through vias, and the semiconductor chip on the inner surface of the lid is bonded to the vias in the lid by TAB strips or (optionally) by wire bonds. The vias in the lid connect these leads through to contacts on the outer surface of the package. These contacts can than be connected to (using interconnect structures such as TAB strips, or printed wiring boards, or discretionary wiring), to provide circuit interconnection. Preferably low-power-dissipation chips are mounted on the inner surface of the lid in this fashion, with higher-power-dissipation chips mounted on the bottom surface of the chip cavity.

Chip carrier with interconnects on lid

A chip carrier including a connecting strip is supported by a thermally conductive spacer block under its center, which provides a mechanical connection to a circuit board. The external contact pads on the underside of the chip carrier are not bonded directly to traces on the board, but instead are bonded to the connecting strip which is formed from a polymer layer having conductive traces thereon. The conductive traces may be bonded to traces on the circuit board.

A chip carrier and mounting structure connected to the chip carrier

A chip carrier is supported by a thermally conductive spacer block under its center, which provides mechanical connection to the circuit board. The external contact pads on the underside of the chip carrier are not bonded directly to the traces on the board, but instead are bonded to a connecting strip, i.e. a polymer layer having conductive traces thereon, and the traces on the connecting strip are bonded to traces on the board.

Circuit board with a chip carrier and mounting structure connected to

The disclosure relates to a photovoltaic solar array which is provided with a matrix having spherical photovoltaic diode particles embedded therein in an ordered array, the P-type region of each particle extending to one matrix surface and the N-type region of each particle extending to an opposed matrix surface. Backside metallization is disposed on the matrix backside surface to interconnect the particles extending thereto and frontside conductors are provided on the opposing matrix surface to interconnect the particles extending thereto. The matrix includes two portions, the first portion being a layer extending to the frontside formed of a clear glass. The second portion of the matrix is, in effect, two layers, one disposed at the P-N junctions of the particles being a lead base glass for junction passivation, this layer being overcoated with a reflective layer to provide additional reflectivity of light entering the matrix onto the particles. This increases the amount of light impinging on the particles. The frontside of the matrix includes a light transparent conductive material with electrically conductive whiskers embedded therein for improved conductivity.

Growing community of inventors

Dallas, TX, United States of America

Charles E Williams