Apple Inc.

Arm Limited

Charles E Tucker

Jeffry E Gonion

Lior Zimet

Mridul Agarwal

Tal Kuzi

Gerard Richard Williams

Richard F Russo

Gideon N Levinsky

Shih-Chieh Wen

Christopher M Tsay

Jeffrey E Gonion

Ali Sazegari

Chris Cheng-Chieh Lee

James Vash

Steven John Fishwick

Erik P Machnicki

Mbou Eyole

Harshavardhan Kaushikkar

Nigel John Stephens

Sergio Kolor

Pradeep Kanapathipillai

Gaurav Garg

Aditya Kesiraju

Srinivasa Rangan Sridharan

Per Hakan Hammarlund

Tyler J Huberty

John H Kelm

Sagi Lahav

Lital Levy-Rubin

Dany Davidov

Nir Leshem

Mark Pilip

Fan Wu

Alex Klaiber

Zhaoming Hu

Gerard R Williams Iii

Chris Cheng-Chie Lee

An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Scalable interrupts

An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

Scalable system on a chip

A method and system for compressing and decompressing data is disclosed. A compression command may initiate the prefetching of first data, which may be stored in a first buffer. Multiple words of the first data may be read from the first buffer and used to generate a plurality of compressed packets, each of which includes a command specifying a type of packet. The compressed packets may be combined into a group and multiple groups may be combined and stored in a second buffer. A decompression command may initiate the prefetching of second data, which is stored in the first buffer. A portion of the second data may be read from the first buffer and used to generate a group of compressed packets. Multiple output words may be generated dependent upon the group of compressed packets.

Hardware compression and decompression engine

Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

Systems and methods for performing memory compression

Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

Systems, apparatuses, and methods for coalescing interrupts temporally for later processing are described. An interrupt controller in a computing system maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts.

Systems and methods for coalescing interrupts

An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory. Decode circuitry is responsive to a single access instruction identifying a plurality of vector registers and a plurality of data structures that are located discontiguously with respect to each other in the memory, to generate control signals to control the access circuitry to perform a sequence of access operations to move the plurality of data structures between the memory and the plurality of vector registers such that the vector operand in each vector register holds a corresponding data element from each of the plurality of data structures. This provides a very efficient mechanism for performing complex access operations, resulting in an increase in execution speed, and potential reductions in power consumption.

Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers

Growing community of inventors

Campbell, CA, United States of America

Charles E Tucker