At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Charles E Stroud

Ronald J Canniff

Alan Howard Matten

Philip C Chao

Kenneth D Mozingo

Sunil K Jain

Duane R Aadsen

An arrangement where a plurality of digital signal processors cooperate in the performance of a digital signal processing function. The processors are interconnected by means of a synchronous network which provides time division multiplexed communication links between processors for communicating intermediate processing results therebetween. The synchronous network includes a plurality of port circuits each associated with one of the processors. The network generates timing signals defining frames of time slots and defining superframes comprising N frames. Each port circuit can control the transmission of digital data from a memory of its associated processor during M1 time slots of each superframe. Each port circuit can also control the writing of digital data to its associated processor during M2 time slots of each superframe. The value of N, the number of frames per superframe, is programmable. The values of M1 and M2 are also programmable for each port circuit.

Digital signal processor synchronous network

Testing of data path circuitry (12) within an integrated circuit chip (10) is accomplished by a test circuit (22) comprised of a Signature Analysis Register (SAR) (30). The SAR (30) generates test signals for input to data path circuitry (12) and compacts response signals produced by the data path circuitry following receipt of the test signals. A blocking circuit (28) blocks an initial one of the response signals from being received by the SAR (30) until the test signals from the SAR have propagated through the data path circuitry (12). Bypass multiplexers (34) multiplex the test signals generated by the SAR (30) with input data normally supplied to the data path circuitry (12) to allow the test circuit (22) to be bypassed during intervals other than testing. Loopback multiplexers (26) are also provided to multiplex the output data of the data path circuitry (12) with the input data received by the data path circuitry (12) to allow for testing of a chain of integrated circuits (10 ) on a circuit board (53).

Built-in self-test (BIST) circuit

A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.

Integrated circuit with memory self-test

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North Aurora, IL, United States of America

Charles E Stroud