Qualcomm Incorporated

Charles E Sakamaki

Gilbert Christopher Sih

Prashant A Kantak

Ming-Chang Tsai

Chienchung Chang

Jian Wei

De Dzwo Hsu

Richard Higgins

John G McDonough

Randeep Singh

Li Feng Zhang

Inyup Kang

Haitao Zhang

Qiuzhen Zou

Sanjay K Jha

Way-Shing Lee

Deepu John

Jian Lin

Quaeed Motiwala

Quizhen Zou

A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Cached memory system and cache controller for embedded digital signal processor

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control

A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.

Application specific integrated circuit (ASIC) for performing rapid

Block normalization processor

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Charles E Sakamaki