Motorola Corporation

Charles E Nuckolls

James R Lundberg

Gary R Morrison

Donald L Tietjen

Frank C Galloway

Kristen L Mason

Jennifer L McKeown

Jeffrey M Polega

Jesse R Wilson

Robert Bradford Cohen

Gerald W Garcia

Peter J Myers

An execution unit ( ) interface protocol allowing flow-through of data, where a function is specified once and the execution unit performs the function for multiple sets of input data. Function execution is pipelined through the execution unit, where an input unit ( ) stores information, while a function logic unit ( ) processes data and an output unit ( ) holds results to be output. The execution unit ( ) allows for data rate distortion, in applications such as data compression, where the amount of data received is different from the amount of data generated as output.

Method for an execution unit interface protocol and apparatus therefor

A multiply and accumulate (MAC) unit ( ) having a multiplier ( ) and an adder ( ) for providing a calculated result of a MAC operation, an accumulator ( ) for storing the calculated result, and a scaler unit ( ) for selecting a subset of the calculated result stored in the accumulator. The scaler unit receives information defining the subset as a predetermined number of contiguous bits and defining the location of the bits with respect to a radix point. In response to a detected error in the selection of the subset, the scaler unit selects a second subset, where the second subset also has a predetermined number of contiguous bits having a different location with respect to the radix point:

Multiply and accumulate unit (MAC) and method therefor

Method for maintaining an execution interval for a task requestor to a DMA. A timer is provided with two counters, one ( ) to maintain the execution interval and the second ( ) to track the execution time of a task in the DMA. Each task has a predetermined execution time allowance. A task acknowledge (TACK) signal enables the tracking. A task request signal (TREQ) is generated during each execution interval until the execution time allowance is completed. The length of the second counter is less than the first counter. In one embodiment, if the first counter expires before the execution time allowance is completed, a task error signal (TERR) is illustrated.

Method and apparatus for controlling task execution in a direct memory access controller

Direct memory access controller (DMAC) ( ) adapted to directly execute C language style FOR tasks assigned by a processor ( ), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) ( ), each to perform an arithmetic or logical operation, and a FOR task controller ( ) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

Direct memory access controller and method therefor

Direct memory access controller (DMA) ( ) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) ( ). A master DMA engine (MDE) ( ) includes a top level state machine ( ) to coordinate a context save state machine ( ), a parse state machine ( ), and a running state machine ( ). An loop control descriptor (LCD) queue ( ) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

A method and apparatus for reducing power associated with acquiring phase-lock between a reference clock signal and an internal clock signal after each exit from a quiescent state by a data processing system. A phase-locked loop (PLL) phase-locks the internal clock signal to the reference clock signal. A set of clock drivers receive an oscillator signal from the PLL and generate a plurality of multi-phase internal clock signals in response thereto. The clock state machine receives a first control signal from the PLL, indicating that the phase-locked loop is re-acquiring phase-lock as a result of the data processing system leaving a quiescent state. The clock state machine suppresses a set of clock state signals to prevent the clock drivers from changing state during the period of time when the phase-locked loop is re-acquiring phase-lock. The invention reduces power consumption associated with acquiring phase-lock by eliminating the power resulting from toggling the clock drivers during each exit from the quiescent state by the data processing system.

Power reduction method and apparatus for phase-locked loop based clocks

A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD, is of a voltage level greater than the minimum voltage level suitable for safely resolving CMOS logic. The power sense signal, when asserted, enables a small, on-chip ring oscillator. An output signal generated by the ring oscillator supplies a clocking signal to the clock drivers and to the clock state machine of the CPU, thereby providing internal clocks to a central processing unit (CPU). A counter counts the number of clock pulses provided to the CPU and disables the ring oscillator and the clock state machine (thereby stopping the internal data-processor clock drivers) when the accumulated number of clock pulses equals or exceeds a predefined number. The predefined number of internal clock pulses is the minimum number of clocks to process a reset condition that resolves all on-chip, CPU state conflicts and contention.

Method and apparatus for power-up state initialization in a data

A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.

Method and apparatus for performing frequency detection

A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Method and apparatus for performing frequency acquisition in all digital

A method and apparatus for performing, after frequency acquisition, phase acquisition and phase maintenance in a digital phase-locked loop 10. A phase detector (12), determines the phase relation of an oscillator output to a reference clock signal, and provides a control signal to a controller (13), indicative thereof. When a subsequent logic state of the control signal provided by the phase detector is equal to an initial logic state of the control signal, the controller (13) increments or decrements a control value initially corresponding to a baseline frequency of the oscillator by the gain value, based upon the logic state of the control signal. When the control signal changes state, phase-lock has been acquired, and a gain value which determines the magnitude of change of the oscillator frequency is decreased. On every subsequent change in the logic state of the control signal, the gain value is decreased, unless at a minimum. If the control signal does not change for a predefined number of cycles, the gain value is increased.

Method and apparatus for performing phase acquisition in an all digital

A data processor has an input synchronizer (10) which is dynamically enabled by a plurality of control signals provided by a user of the data processor. When the plurality of control signals has a predetermined logic level, a bias generator enable circuit (18) enables a bias generator (16). Subsequently, bias generator (16) enables a differential amplifier (12) to synchronize an asynchronous input signal to an operating frequency of the data processor. When the plurality of control signals does not have the predetermined logic level, bias generator enable circuit (18) disables bias generator (16). Subsequently, differential amplifier (12) is disabled and the asynchronous input is not synchronized with the internal operating frequency of the data processor. Therefore, because the user may choose the logic levels of each of the plurality of control signals, the user may dynamically disable input synchronizer (10) to minimize the power consumption of the data processor.

Data processing system having a dynamically enabled input synchronizer

A method and apparatus for implementing a constant gain in a digitally-controlled variable oscillator (DCO) 16 where the frequency of the DCO 16 is controlled via binary-weighted control signals. The frequency of the DCO 16 is modulated via arithmetic increments or decrements to the binary-weighted DCO control signals. The magnitude of the arithmetic increments and decrements defines the gain of the DCO. To maintain a constant gain, regardless of operating point or environment, a phase gain register 15 bit-shifts a current DCO control value by a predefined number of bit positions, thereby determining a phase gain value. The phase gain value defines the magnitude of an arithmetic increment or decrement of the current DCO control value, used to determine the next DCO control value. Since the phase gain register 15 uses a bit-shifted version of the current value of the DCO control, the gain value dynamically tracks all updates to the DCO control value, thereby implementing a constant gain in the DCO 16.

Method and apparatus for determining a constant gain of a variable

An all digital phase lock loop (ADPLL), (10) includes a variable digital oscillator (DCO 16), a phase detector (12), a controller (13) including an incrementor (19) and decrementor (21), and a set of oscillator control registers (22). A frequency tracking circuit (20) is separated from the phase acquisition/maintenance logic circuitry. The frequency tracking circuitry (20) uses an anchor value to maintain and update a DCO control value corresponding to a target frequency of operation of the DCO (16). Updates to the anchor value are facilitated by monitoring recent history of an output control signal (ahead or behind) provided by the phase detector (12). The anchor value is changed to maintain the target frequency of operation of the DCO (16), even in the presence of variations in operating environments.

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Austin, TX, United States of America

Charles E Nuckolls