Hewlett-packard Company

Agilent Technologies, Inc.

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Aptina Imaging Corporation

Hewlett-packard Corporation

Charles E Moore

Richard A Baumgartner

Larry S Metz

James Oliver Barnes

Earl C Herleikson

Benny W H Lai

Zachary Dietz

Alfred F Gort

Robert A Zimmer

Ulrich E Hess

Charles A Brown

Nurwati Suwendi Devnani

Thomas M Walley

Aaron Matthew Volz

Hugh S Wallace

James R Hulings

Duane A Fasen

Jerome E Beckmann

John H Stanback

Winthrop D Childers

Michael John Brosnan

Paul H McClelland

Kenneth E Trueba

Brian J Keefe

Steven Warren Steinfield

Travis N Blalock

Rajeev Badyal

Jeffrey R Rearick

Gunter Steinbach

Brian James Misek

Mark Alan Anderson

Christopher D Silsby

Alvin Leng Sun Loke

Richard Baumgartner

Thomas K Bohley

Ran-Fun Chiu

Barbara Jean Duffner

Robert Keith Barnes

Sui-hing Leung

Christopher Koerner

Brian Jeffrey Galloway

Li Ching Tsai

Ronnie E Owens

Charles Myers

Richard A Baugh

Philip Wilfred Fisher

Ronald R Kennedy

Suzette Denise Vandivier

James M Moore

Ulrich Knoch

James S Ignowski

Matthew M Borg

Charles L Wang

Xiaoyang Zhang

Grosvenor H Garnett

Peter N Lim

Kenneth R Stafford

Michael M Oshima

Jason T Nguyen

Earl C Herlelkson

George C Reick

George C Rleck

Eldukar V Bhaskar

Thorsten Krueger

Donald K Moore

A footwear mat assembly for preventing arthropods from entering footwear stored thereon includes a base including a base top surface including a footwear storage location adapted to receive a pair of footwear, and a raised barrier including a barrier bottom surface adhesively and removably secured to the base top surface, a barrier top surface carrying an arthropod-securing adhesive composition layer, and a barrier inner perimeter defining an opening adapted to receive the pair of footwear therethrough for placement on the footwear storage location.

Arthropod prevention footwear mat assembly

An imaging pixel array and associated method and system are disclosed in which the array contains first pixels each having a first photo-conversion device, and second pixels each having a first photo-conversion device and a second photo-conversion device. The first photo-conversion devices are configured to acquire an image during a first integration period. The second photo-conversion devices are configured to acquire a plurality of images during the first integration period. A circuit uses the plurality of image signals and determines from them relative motion between the array and an image during a portion of the first integration period and provides a signal representing the motion which is used for image stabilization.

Method, apparatus and system for image stabilization using a single pixel array

A linear PLL includes a VCO with first and second tuning elements. The first tuning element is adjusted in proportion to the phase error between an input signal and a VCO signal and the second tuning element is adjusted by an integral function of the phase error. By configuring the VCO with separate tuning elements that are separately adjusted in proportion to the phase error and by an integral function of the phase error, the 3dB bandwidth frequency of the linear PLL depends primarily on the phase detector gain and the VCO gain that is contributed from the proportional adjustment. A linear PLL with separate proportional and integral tuning elements can be designed to exhibit a relatively constant gain over a relatively large frequency range.

Linear phase-locked loop with dual tuning elements

A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage. The second component is configured to adjust a voltage across a capacitor based on the states of the first and second input signals, wherein the voltage across the capacitor comprises the second control voltage.

Low-jitter charge-pump phase-locked loop

A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Integrated circuit package

Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.

Programmable hysteresis for boundary-scan testing

A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

Method for testing jitter tolerance of high speed receivers

Integrated circuit and method of manufacturing an integrated circuit and package

A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.

Method and apparatus for testing a high speed data receiver for jitter tolerance

An LC voltage controlled oscillator for use in a SERDES. The oscillator comprises a pair of cross coupled field effect transistors coupled with a pair of multi-layer inductors.

Oscillator for SERDES

Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Method for synchronizing multiple serial data streams using a plurality of clock signals

Interpolation along an axis is performed on a Correlation Surface Array that was created from counting the instances of difference (XOR) between corresponding pixels of single bit resolution images having trial displacements. The interpolation is performed by finding the intersection of two straight line segments that are identified by the shape of the cross section of the Correlation Surface along the axis of interest. In the case of nine trial shifts there are three values in such a cross section, and they may seen as representing three points whose abscissas are the pixel shift amounts minus one, no shift, and plus one, and whose ordinates are the corresponding correlation values. In situations where navigation (and interpolation) is possible, these three points will have certain properties. The ususal case is that two of the points determine one line having a slope m, and the other point determines the other line (assumed to have slope &minus;m). The three points may also lie along the same line, although this represents an exceptional case that may be handled differently. The three points might also describe other conditions that are associated with Correlation Surfaces that are not suitable for navigation, and these are ignored. In the usual case the point of intersection for the two lines is found and its abscissa is the interpolated value for motion along the axis of interest.

Simplified interpolation for an optical navigation system that correlates images of one bit resolution

Optical navigation upon grainy surfaces whose orientation is inclined at about 45&deg; to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45&deg; and 135&deg; inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a transverse ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations. The direction from which illumination arrives relative to the X and Y axes affects the range of angles (relative to, say, the Y axis) that a filter is effective, by changing the apparent size and proportions of the highlights and shadows that are the perceived features ultimately navigated upon. Stable operation of the control system can be enhanced by ensuring overlap of the filters' ranges, and can be promoted by dynamically altering the direction from which illumination reaches the navigation surface, so that it corresponds to, or varies in relation with, the filter in use.

Image filters and source of illumination for optical navigation upon arbitrary surfaces are selected according to analysis of correlation during navigation

A method and apparatus are provided for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more AC-coupled connections on a printed circuit board (PCB). Direct current (DC)-restore logic receives an AC-coupled signal that corresponds to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.

Method and apparatus for enabling extests to be performed in AC-coupled systems

Growing community of inventors

Loveland, CO, United States of America

Charles E Moore