Sun Microsystems, Inc.

Other

Charles E Molnar

Ivan E Sutherland

Ian W Jones

Scott M Fairbanks

Robert F Sproull

Alan Backus

William Stuart Coates

The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before receiving a Done signal. A Sharing arbiter can be implemented by adding a queue onto the Done input of a Sequencer arbiter. In a Sharing arbiter with a Sharing-number of N and K request inputs, the Sharing arbiter is permitted to issue M grant signals concurrently if M input requests have been received (where M&lE;K and M&lE;N) without enforcing mutual exclusion between the grants if at least M Done signals have also been received. Where less than M Done signals have been received (P Done signals, for example), the Sharing arbiter arbitrates among the M input requests and is permitted to issue P grant signals concurrently.

Sharing arbiter

A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations. Alternatively, the bifurcation circuit may be implemented as a dedicated branch or join circuit. The circuits exhibit simple design, low power consumption low transistor count and easy integration into existing applications.

Asynchronous pulse bifurcator circuit with a bifurcation path coupled to control fifo and first and second subordinate fifo

A one-hot Muller C-element, wherein an event received on each of a plurality of inputs results in an event being output, can be implemented with complementary inputs and a true transistor pair comprising one transistor having a gate coupled to a first true input and another transistor having a gate coupled to a second true input; a true arm comprising the true transistor pair, coupled in series between a complement output and ground, and a true pull-up transistor, coupled between the complement output and a source; a true arm pull-up logic gate, coupled at its inputs to complement input wires of the one-hot Muller C-element and coupled at its output to a gate of the true pull-up transistor; a complement transistor pair comprising one transistor having a gate coupled to a first complement input and another transistor having a gate coupled to a second complement input; a complement arm comprising the complement transistor pair, coupled in series between a true output and ground, and a complement pull-up transistor, coupled between the true output and the source; and a complement arm pull-up logic gate, coupled at its inputs to true input wires of the one-hot Muller C-element and coupled at its output to a gate of the complement pull-up transistor.

One-hot Muller C-elements and circuits using one-hot Muller C-elements

A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as &ldquo;places&rdquo; and &ldquo;paths,&rdquo; and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.

Method and modules for control of pipelines carrying data using pipelines carrying control signals

Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Measurement of signal propagation delay using arbiters

Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element. This feature is possible because the next stage receives at the input Din of latch block the same data element that appears at the input Din of the current latch block when the current latch block is transparent.

Control circuit and method for a first-in first-out data pipeline

An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination of request signals and their complements and grant signals and their complements fed back from the output of the arbiter circuit. At any point in time, only one of the plurality of MUTEX elements is selected based on the current state of the grant signals. The selected MUTEX element is used to arbitrate and grant one user exclusive access to a shared resource among the one or more users requesting exclusive access to the shared resource. All the other MUTEX elements in the arbiter circuit are disabled and are inactive during this time. After issuing the grant signal, the selected MUTEX element is disabled and a new MUTEX element responsible for issuing the next grant signal is selected based the new state of the grant signals.

Asynchronous arbiter using multiple arbiter elements to enhance speed

A technique has been described of characterizing the timing behavior of circuits with multiple input terminals. The technique allows determination of minimum and maximum delays. Additionally, it provides the precise circuit behavior as the relationship among the input signals changes with respect to the average of the input signal times to exhibit domination by the later arriving signal or regimes where the delay is affected by more than one input signal.

System for characterization of multiple-input circuits

A technique is disclosed for interlocking FIFO data paths. The data paths are interlocked using a series of control elements which receive input signals not only from the other control elements of their own path, but also from control elements of an adjacent data path. Queues may also be employed between the FIFO control chains to provide greater freedom in the interlocking mechanism.

Control chains for controlling data flow in interlocked data path

An arbiter circuit is described that is capable of granting a first user access to a shared resource while concurrently arbitrating subsequent requests from the first user to other users seeking access to the shared resource. The arbiter of the present invention includes a first arbiter element and a second arbiter element. The first arbiter element is initially used to arbitrate and issue a grant signal in response to one or more request signals from two or more users. The second arbiter element arbitrates and issues the next grant signal in response to subsequent request signal or signals from the one or other users. In one embodiment of the invention, the first and second arbiter elements are used alternately. In other embodiments, third and fourth arbiter elements are used to arbitrate in response to subsequent requests. The arbiter circuits of the present invention all reduce the delays in the access of users to the shared resource.

A technique is described for transmitting events over three or more conductors in which a sequence of activity of the conductors for information transfer is provided. To transfer information, the conductors are placed in an active state in a sequential manner, and then returned to an inactive state after each has been active in a time period short enough to prevent all conductors from being active at the same time.

Three conductor asynchronous signaling

A counterflow computing pipeline including a series of similar stages is disclosed. In the basic form of the pipeline, the stages are arranged in a linear fashion and each stage in the pipeline communicates with its two adjacent stages. The flow of data elements in the pipeline is bi-directional. A first data stream of data elements flows in a first direction from stage to stage in the pipeline. A second data stream of data elements flows from stage to stage in the pipeline in a second direction counter to the first direction. Circuitry at each stage is provided so that every data element flowing in the first direction meets each and every data element that it passes flowing in the second direction. According to various embodiments of the invention, when two data elements meet at a stage, circuitry may be provided to compare the data elements, copy data from one data element to the other, or otherwise, cause the data elements to interact. The counterflow pipeline may be either synchronous or asynchronous, and may be used for a variety of applications in signal processing, associative memory, and computer architectures.

Cascaded multistage counterflow pipeline processor for carrying distinct

Centralized broadcast of a plurality of computer programs through a point to multipoint communications medium to a plurality of computers able to select, receive and execute computer programs from within said plurality of computer programs. Computer programs to facilitate the purchase of one or more computer programs from within the plurality of computer programs, and the computer programs to facilitate purchase being transmitted through the point to multipoint communications medium.

Growing community of inventors

Webster Groves, MO, United States of America

Charles E Molnar