Advanced Micro Devices Corporation

Lsi Logic Corporation

Other

Lsi Corporation

Advanced Micro Services

Charles E May

Mark I Gardner

H Jim Fulford

Robert Louis Dawson

Frederick N Hause

Fred N Hause

Hemanshu D Bhatt

Derryl D J Allman

Thien T Nguyen

Iraj Emami

Peter Austin Burke

Byung-Sung Kwak

Sey-Shing Sun

David T Price

Homi E Nariman

Robindranath Banerjee

Shafqat Ahmed

David Pritchard

Thomas J Goodwin

Derick J Wristers

Venkatesh P Gopinath

Kuang-Yeh Chang

Tim Z Hossain

John Lee Nistler

Richard W Jarvis

Derryl J Allman

Mark W Michael

Robin W Cheung

Wilbur G Catabay

William S Brennan

Arvind Kamath

Michael P Duane

Sey-Ping Sun

Dim-Lee Kwong

Peter J Wright

Mohammad R Mirabedini

Timothy Z Hossain

Kenneth J Morrissey

H Jim Eulford, Jr

Alan Campion

Mark I Gardener

An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.

Arrangement and method for fabricating a semiconductor wafer

A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Method for redirecting void diffusion away from vias in an integrated circuit design

A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

Method and apparatus for diverting void diffusion in integrated circuit conductors

A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design

A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Method of forming a low k polymer E-beam printable mechanical support

A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Bond pad design

Low k polymer E-beam printable mechanical support

An apparatus for controlling the substrate temperature of a substrate during processing of the substrate at a process energy. A chuck temperature input receives temperature measurements from temperature sensors at a substrate chuck, and a temperature set point input receives temperature set points. The temperature set points define a range of temperatures within which the apparatus maintains the substrate temperature. A chuck temperature controller output sends control signals to a chuck temperature controller, which signals are operable to selectively increase and decrease the chuck temperature. A process energy output sends control signals that are operable to selectively increase and decrease the process energy during the processing of the substrate. A controller compares the temperature measurements received from the temperature sensors at the substrate chuck through the chuck temperature input to the temperature set points received through the temperature set point input. The controller sends control signals through the chuck temperature controller output to the chuck temperature controller to selectively decrease the chuck temperature when the temperature measurements received from the temperature sensors at the substrate chuck are above the temperature set points. The controller further sends control signals through the process energy output to selectively decrease the process energy when the temperature measurements received from the temperature sensors at the substrate chuck are above the temperature set point. Preferably, the controller first sends control signals through the chuck temperature controller output to control the chuck temperature, and only sends control signals through the process energy output when the chuck temperature cannot be sufficiently controlled by the chuck temperature controller.

Temperature control system

Embodiments of the invention include a method for forming copper interconnect structure. The method involves providing a substrate having a copper conductive layer formed thereon. An insulating layer having openings is formed on the conductive layer so that the openings expose portions of the underlying conductive layer at the bottom of the openings. A barrier layer is formed on the surface of the substrate. A portion of the barrier layer is removed at the bottom of the opening to expose the underlying conductive layer. A copper plug is formed in the opening such that the bottom of the plug is in contact with the exposed conductive layer. The substrate can be subjected to further processing if desired. The invention also includes a copper interconnect structure having increased resistance to electromigration.

Via and metal line interface capable of reducing the incidence of electro-migration induced voids

A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO , which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

High performance MOSFET with modulated channel gate thickness

A method of processing a semiconductor wafer and an associated semiconductor wafer arrangement which inhibits &ldquo;punch through&rdquo; and increases the yield of functional semiconductor wafers during the fabrication thereof is disclosed.

Semiconductor wafer arrangement of a semiconductor wafer

An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.

Thermal low k dielectrics

A method of standardizing a fabrication process for an integrated circuit. The fabrication process includes a preceding thermal energy sensitive process and at least one set of selectable succeeding thermal energy delivery processes. An integrated circuit structure is formed using the preceding thermal energy sensitive process. The preceding thermal energy sensitive process is characterized based at least in part upon the greatest amount of thermal energy delivered to the integrated circuit by one of the set of selectable succeeding thermal energy delivery processes. Then as subsequent processes are selected and accomplished, if they do not deliver the greatest amount of thermal energy as anticipated by the preceding thermal energy sensitive process, an additional amount of thermal energy is added, so as to preferably equal the anticipated greatest amount of thermal energy. In this manner, the characterization of the preceding thermal energy sensitive process attains its desired parameters.

Thermal characterization compensation

A dual-damascene process for forming an integrated circuit structure is described. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The exposed portion of the dielectric substrate is subjected to an ion beam to damage the exposed dielectric material. The damaged portion of the dielectric substrate is then removed, such as by etching, thereby forming a via cavity below the trench in the dielectric substrate. Generally, the damaged portion of the dielectric substrate etches at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical. More precise control of via cavity geometry provides for more precise alignment of the via cavity with underlying conductors in the integrated circuit structure.

Ion beam dual damascene process

A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.

Process for improving mechanical strength of layers of low k dielectric material

Growing community of inventors

Gresham, OR, United States of America

Charles E May