Commodore Business Machines, Inc.

Kendall Square Research Corporation

Charles E Hauck, Jr

William F Gardei

A method and processor for evaluating numbers processes components of a pair of input numbers A, B in a plurality of identical gate structures. Each gate structure receives information from two bit positions and operates without carry information or any earlier computations to produce a conditional sum word. A control signal derived from the conditional sum word provides the same evaluation as the actual sum in fewer processing steps. A preferred embodiment produces the sticky bit for a rounding off unit in a floating point processor.

Fast control for round unit

A latch transfers fetched opcode to PLA for execution at the earliest opportunity following execution of a prior single cycle opcode.

Growing community of inventors

Framingham, MA, United States of America

Charles E Hauck, Jr