International Business Machines Corporation

Charles E Drake

John Atkinson Fifield

Howard L Kalter

Scott C Lewis

John Edward Barth, Jr

William Paul Hovis

Daniel J Nickel

James A Yankosky

Claude Louis Bertin

Erik L Hedberg

Barry Joe Wolford

Gordon A Kelley, Jr

Peter Joel Jenkins

Thomas E Obremski

Richard D Wheeler

Mark Adam Beiley

Mark Beiley

Charles H Stapper

Francis Anthony Creed

A small number of redundant circuits are freely allocable to any of a plurality of partitions or systems within an integrated circuit, such as a large dynamic random access memory (DRAM) consistent with the provision of parallel simultaneous refresh of corresponding addresses in all partitions or systems thereof. A valid address of a redundant circuit substituted for a partial address of a circuit in any partition or system is detected to disable refresh of that address in all partitions. The partition in which the substitution has been made is sensed and the disablement of refresh of all other partitions is overridden so that all partitions or systems in which a substitution has not been made may be refreshed concurrently with the substituted redundant circuit.

Partitioned dynamic memory allowing substitution of a redundant circuit

The preferred embodiment of the present invention provides a memory system for use in a computer system that improves the performance of a bit redundancy steering mechanism. The preferred embodiment provides a timing signal path to the bit steering mechanism with a delay shorter than that to the memory data array. Additionally, the required address signals are provided to the bit steering mechanism before the addresses are provided to the memory data array. This is preferably accomplished by bypassing the buffers and providing the address signals directly to the bit steering mechanism.

High performance redundancy in an integrated memory system

A reset circuit for resetting a memory system following a radiation event includes an error detect circuit for producing an error signal in response to detection of an uncorrectable error in the systems memory arrays, and includes a control circuit for selectively resetting at least select portions of the memory system in response to the error detect signal. All or portions of the memory arrays can be reset by the control circuit, and complete or selective latch reset, or selective power recycling are provided. In one embodiment, the control circuit provides latch reset in response to the error detect signal so as to reset the memory latches without recycling power, and in another embodiment, the control circuit selectively cycles power to independent memory zones of the system to reset only those zones whose memory array is identified as having an uncorrectable error. Preferably, the control circuit, and perhaps the detect circuit, are radiation hardened to further ensure dependable operation of the reset circuit following a radiation event.

Memory system reset circuit

In one aspect, a memory device employing device-level error correction tracks the status of the error correction in terms of whether error correction is active or inactive, whether an uncorrectable error beyond the capability of the device-level correction is detected, whether a recovery option from an uncorrectable error is active and whether the recovery option has been reset. In another aspect, a diagnostic method for determining a status for one or more aspects of device-level error correction employed by a memory device is provided. In the diagnostic method, the status is determined for the one or more aspects, a flag is set based on the status, the flag is latched, a diagnostic code is input into the memory device and the latched flag is read.

On-chip ECC status

A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

Dynamic RAM with on-chip ECC and optimized bit and word redundancy

A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned 'on' and 'off' by the input node to supply an output signal to the output node when turned 'on'. A second transistor is provided, the output of which is connected to the output node when turned 'on' to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

CMOS driver circuit

Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission gate systems being coupled to a different one of the second given number of decoders, and second control circuits for selectively activating the first and second gates of each of the second plurality of transmission gate systems.

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Underhill, VT, United States of America

Charles E Drake