Intel Corporation

Charles E Dike

Jerry G Jex

Keith M Self

Shay Gueron

Martin Guy Dixon

Jesse R Walker

Stephen R Mooney

Shekhar Yeshwant Borkar

Nasser A Kurd

Ernie F Brickell

Stephen Anthony Fischer

Howard C Herbert

David Johnston

Javed Sabir Barkatullah

George W Cox

James S Coke

David Joseph Hawkins

Mark E Schuelein

Craig B Peterson

Edward V Gamsaragan

Bradley A Bloechel

Jim Sutton

Gunendran Thuraisingham

Greg W Piper

Robert Gatlin

An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.

Latch with a feedback circuit

A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source 'extra' bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Digital random number generator using partially entropic data

In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed.

Controlling transmission on an asynchronous bus

A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

Circuit to manage and lower clock inaccuracies of integrated circuits

An apparatus includes at least one logic storage unit which has a clock input. The apparatus also includes a logic circuit associated with the at least one logic storage unit. The logic circuit is capable of selectively preventing a clock signal from being applied to the clock input of the at least one logic storage unit.

Apparatus and method for reducing power consumption by a data synchronizer

Embodiments of the present invention include a two-dimensional C-element array that may be configured to propagate a periodic waveform. The two-dimensional C-element array is advantageous in high-speed clocking applications as in, for example, processors in semiconductor chips.

Two-dimensional C-element array

A device and method for improving the synchronization and metastability resolving capabilities of a flip flop. At least one master latch resolves a metastable condition of a received data signal thereby generating a stable data signal which is received and then displayed by a slave latch. Latches with superior metastability time resolution are configured in a master-slave relationship along with a novel clocking scheme whereby the clock signal supplied to the master latch is inverted as compared to that which is supplied to slave latch. As a result, the input data is latched on a falling edge of a clock signal and subsequently displayed on the rising edge of the clock signal providing at one half cycle for the input data to settle before passing out the data thereby allowing metastabilities to resolve during that period.

Long setup flip-flop for improved synchronization capabilities

An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.

Backgate biased synchronizing latch

A method and apparatus for minimizing a disparity of set and clear bits transmitted across a serial line is disclosed. The method operates by determining a line disparity by examining n-bit datawords that are transmitted. The method also determines a dataword disparity is determined for a dataword yet to be transmitted. The dataword yet to be transmitted is then inverted before transmission if the line disparity and the dataword disparity have the same sign.

Method and apparatus for reducing the disparity of set and clear bits on a serial line

In a computer system having multiple components, a bidirectional scheme which allows bidirectional data communications between components over a single wire without using termination resistors by placing two drivers from two corresponding processor cores on the same wire, and allowing simultaneous data transfer in two directions. This doubles the effective bandwidth per pin without requiring a modification to the clocking scheme of the system. The driver is impedance matched to the line, and used as the termination for the driver on the opposite end of the wire. This reduces the termination power, since no power is consumed when both drivers are in the same state. The bidirectional flow of data creates a ternary encoding, with a relatively simple decoding possible.

High speed bidirectional signaling scheme

A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.

Fully asynchronous interface with programmable metastability settling

An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.

Asynchronous interface between parallel processor nodes

A data transfer system includes a buffer for storing data to be transferred out of the buffer and a register circuit coupled to the buffer for receiving the data from the buffer. The buffer generates a first indication signal when the buffer is almost empty. The buffer generates a second indication signal when the buffer is empty. The register circuit generates a request signal to receive the data from the buffer. The data transfer system further includes a throttling circuit coupled to the buffer and the register circuit for throttling data transmission to the register circuit from the buffer when the buffer generates the first indication signal and for stopping data transmission to the register circuit from the buffer when the buffer generates the second indication signal. The throttling circuit receives the first and second indication signals and the request signal. The throttling circuit maintains maximized data transfer rate between the buffer and the register circuit while immediately stopping the data transfer between the buffer and register circuit when the buffer is empty.

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Hillsboro, OR, United States of America

Charles E Dike