Qualcomm Incorporated

Charles David Paynter

Ryan David Lane

Yue Li

Ruey Kae Zang

Siamak Fazelpour

Li-Sheng Weng

David Ian West

Hong Bok We

Michael J Brunolli

Aniket Patil

Chin-Kwan Kim

Vaishnav Srinivas

Xiaonan Zhang

Jianwen Xu

Shree Krishna Pandey

Zhongping Bao

John D Eaton

William Michael Stone

Xiaoming Chen

Biancun Xie

Amit Mano

Durodami Lisk

Bernie Jord Yang

Eric David Foronda

A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

Package comprising channel interconnects located between solder interconnects

Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

Providing a lower inductance path in a routing substrate for a capacitor, and related electronic devices and fabrication methods

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Package comprising integrated devices coupled through a metallization layer

A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate

A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.

Patch substrate configured as a shield located over a cavity of a board

An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

Integrated circuit (IC) module comprising an integrated circuit (IC) package and an interposer with embedded passive components

Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

Staggered power structure in a power distribution network (PDN)

A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

Toroid inductor with reduced electromagnetic field leakage

Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

Inductor embedded in a package substrate

Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Method and apparatus for routing die signals using external interconnects

The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

Apparatus and methods for shielding differential signal pin pairs

A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package.

Systems and methods for thermal dissipation

Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

DC/ AC dual function Power Delivery Network (PDN) decoupling capacitor

Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.

Package on package (PoP) integrated device comprising a redistribution layer

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

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Encinitas, CA, United States of America

Charles David Paynter