Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Charles D Waggoner

Raffaele Zambrano

Antonio Imbruglia

Gary B Kotzur

Richard J Blumberg

An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit. The conductor includes at least one fold for extending the length of the conductor to exceed the distance between the input bonding pad and the receiver input node.

Integrated circuit with improved electrostatic discharge protection circuitry

Integrated circuit with improved electrostatic discharge protection

A tri-state I/O buffer and a method of inhibiting current to an I/O buffer arranged to be powered by a supply voltage and to drive an output terminal are provided. The I/O buffer preferably has an output driving circuit connected to the supply voltage for driving the output terminal and includes a first plurality of transistors defining an isolated floating well circuit for operatively connecting the output terminal to the supply voltage and a second plurality of transistors defining a pull-down circuit for operatively connecting the output terminal to ground. An input control circuit is connected to the output driving circuit and the supply voltage, and is arranged to receive a buffer input signal for controlling the buffer input signal to the output driving circuit. A bias controlling circuit is connected to the isolated floating well circuit and the supply voltage, and is arranged to receive a tri-state enabling signal and the buffer input signal for controlling a biasing signal to the floating well circuit.

Current inhibiting I/O buffer having a 5 volt tolerant input and method

A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V.sub.DD voltage level during normal operation, and clamp the special rail to the V.sub.SS rail upon the occurrence of an overvoltage event. Input bonding pads are provided along each edge of the chip and are connected through diodes to the special rail so that 5 volt signals applied to the input bonding pads do not cause damage to the device when operated from a 3.3 volt supply. A signal line of extended length is provided between each input bonding pad and its receiver circuit and includes folded portions for adding to the length of the signal line to form a high frequency inductor to protect the receiver circuit at the onset of an overvoltage event before clamping becomes effective.

Integrated circuit with improved overvoltage protection

A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.

Receiver circuit with a bus-keeper feature

A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.

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Richardson, TX, United States of America

Charles D Waggoner